Intel's Core architecture cannot scale with clockspeed
The fundamental problem with Intel's architecture is the FSB bottleneck. This is well understood.
As Intel increases the clockspeed of its CPUs, it hits two walls. The first is the heat density -- Intel CPUs are running at high temperature -- near the edge of silicon meltdown. The second is the FSB -- Intel systems simply do not have the bandwidth to handle the demand of modern multitasking computing paradigm.
As Intel increases the clock speed by going to 45nm, the CPU tries to do more, but the FSB is the limiting factor. With Intel's primitive design, all communications, even core-core cache coherence traffic have to funnel through the front side bus. Thus, it is entirely possible that Intel CPUs demonstrate lower performance at higher clock speed, due to the fact that higher frequency Intel CPUs generate more traffic jam on the bus. We have seen SpecInt_rate benchmarks where a 1.86GHZ Intel quad is faster than a 2.13 GHZ Intel quad. We identified the cause of the problem to the cache size, but the real fundamental problem is bandwidth limitation. Intel uses large caches to hide its bandwidth constriction for small benchmark programs. In real applications where memory and bandwidth requirements are higher, Intel architecture is simply choked.
I heard that a professor lecturing in computer architecture at the Tel Aviv University gave Intel engineers a C+ on the Core 2, largely due to the double cheeseburger multi-core design.