With new architecture, Intel will be four generations behind AMD
After three years of hard work, Intel seem have made a major improvement in its next generation Conroe/Merom CPUs: its implementation of AMD64 instruction set is looking good, unlike EM64T in Pentium 4, which is about 10-20% slower than 32 bit mode.
However, 64 bit was just one of the five disruptive technologies AMD introduced with Opteron. Intel's new architecture will still be four generations behind AMD.
An AMD CPU consists of two major functional parts: execution and communication. AMD CPUs have circuits for Core-Core communications (XBAR), Processor-Processor communications (ccHT), Processor-I/O communications (HT) and Processor-Memory communications (IMC). The communication channels are dedicated and separate from each other. Also, since these communication circuits run at CPU's clockspeed, they have very high performance and consume little power. The communication circuits are also very intelligent, for instance, ccHT establishes a single physical memory space from multiple memory banks controlled by different CPUs.
Intel CPUs have none of the above. In Intel architecture, all communications happen on an external shared bus controlled by an external chipset manufactured on 130nm process. The fastest future Intel bus has a bandwidth of 10.6GB/s, less than the bandwidth required for DDR2 800MHZ(12.8GB/s). If you add a couple of GbEs and SATAII drives to an Intel system, you are jamming the bus. When you add more Intel cores, you are choking the bus. An Intel quadcore system will be like an IBM XT connected to a 2400baud modem.
We expect AMD to continue to innovate on both execution and communication with its next generation processors.