Tuesday, January 02, 2007

2007 the year of total domination

Time flies. It's 2007 and we are only a few months away from true quad core. With 8 sockets, you will see affordable 32 way (8x K8L) AMD64 computing. Against this 32way monster, Intel is stuck at 8 cores (2x Clovertown) struggling for a 1333MHZ FSB.

If we reveiew the situation since the beginning of time, AMD and Intel had always been in a close race. But, that is going to change in 2007. For the first time, AMD will enjoy a 4x performance lead in servers. In desktop, its lead will be 2x with K8L Quad FX.

As x86 systems getting more and more powerful, the RISC pie will shrink more.

40 Comments:

Blogger Jeach! said...

Happy new year to everyone (yes, Intel fans too)!

Sharikou you still didn't answer by a simple 'yes' or 'no' on wether you have or will be receiving a free AMD/Windows laptop? And if you have or will be, are you going to disclaiming this fact?

And now for my post...

I'm glad to see that AMD will be taking a huge lead in 4-way and 8-way computing.

But there are a few things which I don't quite understand, which some of you may have a simple answer to.

1. Why will it take Intel so long to integrate the memory controller on die?

2. Why will it take till 2009 for Intel to release its own HT bus?

3. Why will it recently be releasing a 4-way solution but it won't be able to go any higher than that for many years?

To me it makes no sense (but certainly glad) that it would take Intel so long. Aren't problems always a matter of how much money you throw at them? What if Intel puts all the money it has on this... how soon can it come up with a computing solution to all of the above issues?

1:14 PM, January 02, 2007  
Blogger Core2Dude said...

Hey Sharikou,

Happy new year! Congratulations on keeping the rambling up. I mean, what could be more hopeless for AMD? 65nm is just starting, with those chips performing worse than their 90 nm counterparts. Intel is ramping up like crazy, selling P4s for dirt cheap (with which the 65 nm has to compete). Core 2 is annihilating AMD on every front (except 4 way), and Intel 45 nm will probably be here before k-late. Also, the k-late won't ramp till next year, when it will have to go against Nehalem.

Take care and keep up the spinning. We enjoy it.

--Core2Dude

1:21 PM, January 02, 2007  
Blogger Sharikou, Ph. D said...

Sharikou you still didn't answer by a simple 'yes' or 'no' on wether you have or will be receiving a free AMD/Windows laptop? And if you have or will be, are you going to disclaiming this fact?


I have not yet received my free Acer laptop, they should have sent one to me, but they did not. I will let you know if they will have sent it.

Cheers!

1:27 PM, January 02, 2007  
Blogger Sharikou, Ph. D said...

1. Why will it take Intel so long to integrate the memory controller on die?

2. Why will it take till 2009 for Intel to release its own HT bus?

3. Why will it recently be releasing a 4-way solution but it won't be able to go any higher than that for many years?


I answered these questions long long time ago. AMD is a server CPU company, Intel is a desktop CPU company. Thus the difference. If you look at AMD architects, they all come from server background. Intel has no such expertise -- even their Itanium folks have joined AMD.

1:31 PM, January 02, 2007  
Anonymous Anonymous said...

"I answered these questions long long time ago. AMD is a server CPU company, Intel is a desktop CPU company. Thus the difference. If you look at AMD architects, they all come from server background. Intel has no such expertise -- even their Itanium folks have joined AMD."

LOL. I love pointing this stuff out. This is a "man" who claims to be a ph.d, yet he can only type sentences in broken english.

Tell me Sharikook, where is your degree from? What was your thesis on? Where is it published so we may see more shining examples of your litarary compentency.

BTW, Intel's been putting processors in servers for many many years now, since before the opteron was released or before anyone even considered using AMD inside of a server. Get your stories straight.

1:43 PM, January 02, 2007  
Anonymous Anonymous said...

"I have not yet received my free Acer laptop, they should have sent one to me, but they did not. I will let you know if they will have sent it.

Cheers! "

The sudden use of the word "Cheers!" does not help you gain any credibility - it just makes you look like you're trying too hard...

As to why you didn't, and won't, get a free laptop - it's simple - they only send them to REAL journalists and sites who will actually benchmark the things and report accurate results. Not dimwitted wannabe's who lie about their education level (HS is about as far as you've gotten I'm guessing) and make things up to try and sway people to their pathetic reasoning and mediocre points of view.

Cheers!

1:46 PM, January 02, 2007  
Anonymous Anonymous said...

server CPU company as u name it, does not work on HT chipset which will eliminate cache snoop traffic. even now on 16 cores systems snoop traffic eats 80% of HT bandwidth, thats the reason why nobody except SUN ships 8 socket systems on AMD.

with 32 cores it will be even worse (HT3.0 which can delay snoop traffic collapse is delayed until 2008).

unlike AMD, Intel already announced chipset with snoop cache for 2007.

so its not that simple as you think.

2:05 PM, January 02, 2007  
Blogger osgeek said...

Looks like Intel Core duo is selling well. AMD should come out with a good chip. Native Quad-core will be good provided it comes on time. Funnily, Sun released a native 8-core 32-thread processor Niagara more than a year ago, while the ace processor companies are still struggling to come out with quad-core chips. Looks like Sun will continue to lead for multicore chips for some time to come. Nevertheless, x86 multicore chips will have its own market and the competition between Intel and AMD will be interesting to watch. Waiting for another good processor from AMD... after Opteron it hasn't brought out anything interesting.

3:05 PM, January 02, 2007  
Blogger Core2Dude said...


I answered these questions long long time ago. AMD is a server CPU company, Intel is a desktop CPU company. Thus the difference. If you look at AMD architects, they all come from server background. Intel has no such expertise -- even their Itanium folks have joined AMD.

So goes the FUD-boy again without answering the question. Jeach, let me answer your questions for Sharikou.

It takes 4 to 5 years for any company to come-up with a new CPU layout (starting from the requirements gathering phase). Integrated memory controller and a point-to-point interconnect (CSI/HT) are major changes that cannot be addressed without a new layout of the CPU. Intel was sitting on its @$$ until 2003, happily enjoying the better bin splits they were getting compared to AMD. But in 2003, when AMD K8 came out, suddenly the floor under Intel's bottom got replaced with a hot plate, and Intel started onto the processor called "Whitefield". Whitefield was to be designed in India, and was supposed to have integrated memory controller and HT. However, being a new CPU, it would take 4 years to complete, and hence it was not expected to arrive until 2007.

However, the Indian team screwed up, and Whitefield had to be cancelled. That transferred the pressure of IMC and CSI onto NHM, which does not arrive until middle 08.

In short, ignoring the market and bad execution has gotten Intel into the mess regarding IMC and CSI.

But guess what: there are multiple ways to skin the cat, and Intel is doing just that by throwing large and fast caches and smart prefetchers at the problem. And in fact, they do work. Core 2 annihilates K8.

K-late will put band-aid on AMD's wounds, but nothing like the skin transplant that they need.

4:24 PM, January 02, 2007  
Blogger Core2Dude said...


Funnily, Sun released a native 8-core 32-thread processor Niagara more than a year ago, while the ace processor companies are still struggling to come out with quad-core chips.

Come on now!. A dual-processor woodcrest eats this 32-threaded "monster" for breakfast on most server benchmarks. Core count is not everything. You also have to consider what each core is capable of. Intel and AMD cores are light-years ahead of the Niagara cores, when it comes to single-threaded performance. With Woodcrest DP, you get four extremely powerful cores. With Niagara, you get eight mediocre cores. Guess what, Woodcrest DP costs much less.

4:32 PM, January 02, 2007  
Anonymous Anonymous said...

"Aren't problems always a matter of how much money you throw at them?"

How much money did Intel throw at ThermonuclearBurst, sorry, NetBurst???

5:02 PM, January 02, 2007  
Anonymous Anonymous said...

Well Intel Fanboys, once K8L launches, it's bye-bye Core2Dud!

5:08 PM, January 02, 2007  
Anonymous Anonymous said...

Yes, Nehalem is due in 2008. It will be the next micro-architecture from Intel, and will have the memory controller intergrated into the processor, and will use CSI instead of the FSB.

In 2007 Intel still has Tigerton coming out - quad core servers for 4P and up (up to 32P I believe), as well as a whole new load of 45nm CPUs based on an enhanced Core 2 design.

Lets see a 32P quad core Tigerton system in action. What will AMD do about that!? This will be a move to keep AMD at only 25% of Intel's performance permanently. Everyone knows that crappy 8P is only for ultra low end. AMD is doomed. AMD will be BK by Q2 '08.

Did I do a good enough job of impersonating Sharikou? lolol

6:04 PM, January 02, 2007  
Anonymous Anonymous said...

I agree with Scientia that sometimes, AMD just keeps getting bad press for small minor hiccups while Intel gets away with much bigger problems.

For instance, the cache latency only manifests itself in some tests but for the most part is invisible. The understanding is that it is to cater for larger caches in future.

When Intel moved for Pentium M to Core 2, the switch to shared caches increased cache latency by 40% (if I remember correctly), definitely a larger premium than with the AMD's 65nm. Was there a huge outcry then? Geez.

7:06 PM, January 02, 2007  
Blogger Sharikou, Ph. D said...

I agree with Scientia that sometimes, AMD just keeps getting bad press for small minor hiccups while Intel gets away with much bigger problems.


Intel has a market cap of $100 billion, a lot of losers own that stock and will do everything they can to bash AMD to death.

7:34 PM, January 02, 2007  
Anonymous Anonymous said...

"When Intel moved for Pentium M to Core 2, the switch to shared caches increased cache latency by 40% (if I remember correctly), definitely a larger premium than with the AMD's 65nm. Was there a huge outcry then? Geez."

No outcry because the transition from Dothan to Yonah increased perfromance between 16% to 40% on apps. This was not just a dumb shrink from 90nm to 65nm but also alot was added that enabled this performance increase, not to mention that they were also going from single core to dual core. Intel then increased perfromance even further when they went to Merom.

8:06 PM, January 02, 2007  
Anonymous Anonymous said...

"When Intel moved for Pentium M to Core 2, the switch to shared caches increased cache latency by 40% (if I remember correctly), definitely a larger premium than with the AMD's 65nm. Was there a huge outcry then? Geez."

Intel's switch from P-M to C2 cache latency never showed up in real test like games if they would of then sharikou would of been all over it like stink on... well you know what. Something is up when you do a straight shrink down to the exact amount of transistors and performance decreases by 5%. It must be that extra cache they have planned for the future...I guess.

8:17 PM, January 02, 2007  
Blogger Core2Dude said...


When Intel moved for Pentium M to Core 2, the switch to shared caches increased cache latency by 40% (if I remember correctly), definitely a larger premium than with the AMD's 65nm


Completely untrue! Yonah L2 latency is 14 cycles vs Dothan's 10 (so that is 40%). But AMD's latency is 20 cycles on 65 vs 10 on 90. That is 100% slowdown.

Also, with Yonah, Intel doubled the cache (and with Merom, it made it 4x) and increased frequency. Additionally, shared cache means added load on read/write. So no, Intel's loss doesn't even come close to what AMD has lost.

With 65nm, AMD kept the cache size the same (they may increase it in future) and lowered the clock speed. Additionally, the cache is still split across the cores.

8:30 PM, January 02, 2007  
Anonymous Anonymous said...

"Well Intel Fanboys, once K8L launches, it's bye-bye Core2Dud!"

Core2Dud huh, Amd must of slashed their prices by 75% because they don't like making money. I love how you guys get all emotionally involved with electronics. Seriously, if you guys would pay half as much attention to women parts as you do to computer parts then you wouldn't be so cranky ;)

8:41 PM, January 02, 2007  
Anonymous Anonymous said...

Ho Ho Ho,

Out with the old in with the New Year..

Here is a new one for the PhD pretender

"I answered these questions long long time ago. AMD is a server CPU company, Intel is a desktop CPU company. Thus the difference. If you look at AMD architects, they all come from server background."

Lets look at the profits from the famous server companies; SUN, DEC, or if you go further back that mincomputers companies ...

Ho Ho HO, did they have the profits and volumes to sustain their business? NOPE!! Only IBM with the software business can continue.

AMD is finished without a viable desktop volume product to compete. Giving away Opetron at < 100 bucks is not a winning proposition is a BK strategy

Ho Ho HO happy new year Sharikou same old BS from the pretender

8:45 PM, January 02, 2007  
Anonymous Anonymous said...

When Intel moved for Pentium M to Core 2, the switch to shared caches increased cache latency by 40% (if I remember correctly), definitely a larger premium than with the AMD's 65nm. Was there a huge outcry then?
Wrong.

AMD 90nm L2 latency = 12
AMD 65nm L2 latency = 20
20/12=1.667. +66.7% latency
+8 cycles

Intel Dothan 90nm L2 latency = 10
Intel Yonah 65nm L2 latency = 14
14/10=1.40000. +40% latency.
+4 cycles

8:49 PM, January 02, 2007  
Anonymous Anonymous said...

"Intel has a market cap of $100 billion, a lot of losers own that stock and will do everything they can to bash AMD to death. "

Is this your ph. d talking? Everyone that I know with a Ph. D uses childish name calling to make points...oh wait - no they don't....so you prove yet again you lie.

8:57 PM, January 02, 2007  
Anonymous Anonymous said...

"For instance, the cache latency only manifests itself in some tests but for the most part is invisible. The understanding is that it is to cater for larger caches in future."

This makes no sense - AMD already (on a 90nm process no less) was able to support double the current cache - remember the K8 was able to support 1MB/core vs the current 512KB/core at the same latency.

So if this added latency is to support larger cache, how much are they planning? 2 MB/core? Also why do this for the K8 architecture when K8l is due out in a few months? Finally with 65nm they should be able to address latency issues better due to shorter physical dimensions, unless RC delay is killing them (dielectric issue on the 65nm process?)

Why do people keep saying that the added latency is to support larger cache...if this is really the case why not take the latency hit when you actually put in the larger cache as opposed to taking the hit when you still have the small cache...this "theory" just makes no sense.

10:15 PM, January 02, 2007  
Anonymous Anonymous said...

"For instance, the cache latency only manifests itself in some tests but for the most part is invisible. The understanding is that it is to cater for larger caches in future."

The problem is that it seems to be visible in games and invisible in benching programs, ie real world it suffers compared to it's 90nm brother.

Catering for larger cache in the future? I assume more than 1MB then, which is strange because AMD fan have always said K8 does not need large cache. Indeed, it seems to get away quite well with 512KB rather than 1MB, so why would you need 2MB when you have K8L coming out soon and surely K8 will be bottom feeding?

10:20 PM, January 02, 2007  
Anonymous Anonymous said...

FREE INTEL P4’s;Do you wanta know what Intel really does with its warehouses full of P4's

http://www.consumeroffersource.com/?as=29999&sel_card=962

10:22 PM, January 02, 2007  
Anonymous Anonymous said...

Why do people keep saying that the added latency is to support larger cache...if this is really the case why not take the latency hit when you actually put in the larger cache as opposed to taking the hit when you still have the small cache...this "theory" just makes no sense.

Because AMD said that's why they used higher latency cache.

11:42 PM, January 02, 2007  
Anonymous Anonymous said...

"Because AMD said that's why they used higher latency cache."

Oh, my bad - it must be true then... and where exactly can one find this extra cache on the K8 roadmap? (note: I said K8, not K8l)

Again, why hurt the latency now instead of in the future when they actually plan to put the cache in...it makes no sense if you stop and think about it, rather than just accepting it because someone said it...

12:13 AM, January 03, 2007  
Anonymous Anonymous said...

^No one read the inquirer?

"The quad core will be based on Altair FX core and is scheduled for Q3 next year, so AMD will have to survive for a long time without a real quad core. This one will end up clocked between 2.7 and 2.9GHz and will have 2MB dedicated L2 plus 2MB shared L3 cache.

6:52 AM, January 03, 2007  
Anonymous Anonymous said...

See this:- http://anandtech.com/cpuchipsets/showdoc.aspx?i=2893&p=3

Updated: AMD has given us the official confirmation that L2 cache latencies have increased, and that it purposefully did so in order to allow for the possibility of moving to larger cache sizes in future parts. AMD stressed that this wasn't a pre-announcement of larger cache parts to come, but rather a preparation should the need be there to move to a vastly larger L2. Thankfully the performance delta isn't huge, at least in the benchmarks that we saw, so AMD's decision isn't too painful - especially as it comes with the benefit of a cooler running core that draws less power; ideally we'd like the best of all worlds but we'll take what we can get. Note that none of AMD's current roadmaps show any larger L2 parts (other than the usual 2x1MB offerings), which tells us one of two things: either AMD has some larger L2 parts that it's planning on releasing or AMD is being completely honest with the public in saying that the larger L2 parts will only be released if necessary.

7:27 AM, January 03, 2007  
Anonymous Anonymous said...

"..if you guys would pay half as much attention to women parts..."
Which parts would those be??
And are they overcockable, sorry, overclockable?

8:50 AM, January 03, 2007  
Blogger Core2Dude said...


Oh, my bad - it must be true then... and where exactly can one find this extra cache on the K8 roadmap? (note: I said K8, not K8l)

Again, why hurt the latency now instead of in the future when they actually plan to put the cache in...it makes no sense if you stop and think about it, rather than just accepting it because someone said it...


AMD told Anand that the extra latency is for added cache. AMD also told them that there were no extra-cache parts on the roadmap, and the provision was just in case they needed the added cache.

I do not know much about layout. Can adding to cache latency require new layout? If that is the case, then AMD's argument is reasonable.

However, as many good folks pointed out here, it doesn't make a lot of sense to provision K8 with extra cache (unless of course, AMD is planning on riding that horse for quite some time).

9:53 AM, January 03, 2007  
Blogger TheKhalif said...

server CPU company as u name it, does not work on HT chipset which will eliminate cache snoop traffic. even now on 16 cores systems snoop traffic eats 80% of HT bandwidth, thats the reason why nobody except SUN ships 8 socket systems on AMD.

with 32 cores it will be even worse (HT3.0 which can delay snoop traffic collapse is delayed until 2008).

unlike AMD, Intel already announced chipset with snoop cache for 2007.

so its not that simple as you think.



Can you say shared L3? That's why it is being implemented so that cache snoops can be cut down.

11:11 AM, January 03, 2007  
Blogger osgeek said...

Come on now!. A dual-processor woodcrest eats this 32-threaded "monster" for breakfast on most server benchmarks. Core count is not everything. You also have to consider what each core is capable of. Intel and AMD cores are light-years ahead of the Niagara cores, when it comes to single-threaded performance.

whoa! comparing a chip like Niagara which is meant for throughput and not single thread performance is not wise! The single thread numbers will be better for Niagara 2 which has a floating point unit for each core unlike Niagara which has only one FPU with all 8 cores sharing.
For single thread performance you have to compare Woodcrest with UltraSparc 1V+ that can be scaled upto 144 cores, which is not what you can say about Woodcrest.
The point was how Intel and AMD which just make chips lag behind Sun which has hands full with things like Servers, Solaris, Java, OpenOffice. The processor-focussed companies should be the ones ahead in such innovations, which they are not!

3:34 PM, January 03, 2007  
Anonymous Anonymous said...

"..if you guys would pay half as much attention to women parts..."
Which parts would those be??
And are they overcockable, sorry, overclockable?

I've never met one that you can't overcock...I mean overclock.

3:42 PM, January 03, 2007  
Anonymous Anonymous said...

"However, as many good folks pointed out here, it doesn't make a lot of sense to provision K8 with extra cache (unless of course, AMD is planning on riding that horse for quite some time)."

This is my point - why increase the latency now on the small cache parts? AMD, in their own press release, acknowledges that the latency is worse and says we may need it in the future so to hell with people buying the current parts. Noone has been able to give a single reasonable explanation as to why you would take the latency hit now instead of at the time you actuall do make the cache larger?

AMD clearly has an issue with latency that they could not get corrected straight away and are passing this off on some bogus potential roadmap idea (which is NOT ACTUALLY on their roadmap).

And the beauty is the idiot review sites don't actually no any better (or at least know the right people to ask) to call bullshit on this. I mean I can understand the fanbois eating this up, but you think someone who publishes this crap (like Anand for example) would not publish this BS explanation without asking some hard technical questions to confirm this is plausible explanation first. Even putting in 2MB cache per core should not lead to a substantial hit on latency unless there is an issue with their 65nm process. Obviously 1MB/core worked fine with no latency hit on 90nm technology and given the smaller path lengths on 65nm they should be able to scale this another ~50% with no issue (1.5MB). Now someone explain to me why it is >60% worse based on anything in the layout/design (i.e not an RC, ILD/interconnect process capability issue)?

9:36 PM, January 03, 2007  
Blogger Core2Dude said...


The point was how Intel and AMD which just make chips lag behind Sun which has hands full with things like Servers, Solaris, Java, OpenOffice. The processor-focussed companies should be the ones ahead in such innovations, which they are not!


No! The point is, four Woodcrest cores (2 CPUs) eat Niagara for breakfast on most server benchmarks, while they cost a lot less. Comparing CPUs by number of cores is almost same as comparing them based on megahertz. Intel and AMD are delivering what people want in volume--server CPUs with blazing single-threaded as well as multi-threaded performance. ST performance is important because many people want to make workstations out of them. And while making a new CPU layout for 100,000 some CPUs might be a good exercise, it is hardly a sound business practice.

10:36 PM, January 03, 2007  
Anonymous Anonymous said...


Try looking at stock charts of more than 1 year view....and then appologize to all the Intel share holders that bought at over $75, then at almost $40, then at $35, then again at $28 and are now sitting at $20...wow, that is soooo much better than AMD. Oh, by the way, a bunch of those people work at Intel.


Ever heard of the Dot-com bubble? Are you seriously trying to make me believe that Intel was the only company effected by that? AMD was up near $50 back in 2001 too!

8:41 PM, January 04, 2007  
Blogger Scientia from AMDZone said...

does not work on HT chipset which will eliminate cache snoop traffic. even now on 16 cores systems snoop traffic eats 80% of HT bandwidth, thats the reason why nobody except SUN ships 8 socket systems on AMD.

Sorry, but this is wrong. The problem with an 8-way system is transfer latency, not snoop traffic. K8 has no snoop traffic. This statement shows a serious lack of technical understanding of the difference between AMD and Intel cache protocols.

Intel maintains cache coherency by broadcast and bus snooping (not cache snooping). Since this can amount to a lot of traffic it is desirable to use a broadcast filter when you have more than one FSB. This prevents broadcast traffic from being forwarded to other buses when it is not related. In order to tell what is and what isn't related you maintain a buffer which shows what memory area is being used by which bus. This is essentially a cache directory for the northbridge.

AMD however doesn't have this problem because each processor has its own dedicated memory range and it uses MOESI instead of MESI. This does not require broadcast. In fact, I'm a bit stunned how completely backwards the comment was. When any processor on a shared bus wants to load a memory location it has no way of knowing if another processor has those contents in its cache. So, all processors have to snoop the bus and detect this attempt at access. If another procecssor has this address range in its cache it sends a hold message to allow the cache to be written out to memory first.

K8 does not have difficulty. Why? Because each processor has its own memory. When a processor accesses its own memory it knows that all of the data is available and no broadcast is required. The only time this is needed is if another processor has requested data from its memory range. However, if this has happened it is also recorded in the cache in the issuing processor. If you don't understand anything else about K8, understand that K8 does NOT broadcast on a memory access and does not snoop memory accesses as Intel processors must do. The ONLY traffic that is transferred over HT is when one processor needs something from the address range of another processor or when one processor wants to access a memory location in its own memory space and that range is currently being used by another processor. This volume of traffic is only a fraction of what Intel sees.

The true advantage of DC 2.0 has nothing to do with bus snoop traffic (which is nonexistent). The actual advantage is to reduce HT latency by shortening the number of hops between processors.

The only possible way you could get 80% saturation would be to run K8 with a non-NUMA OS so that each processor will be constantly requesting data from the other's memory range.

8:24 AM, January 05, 2007  
Blogger Scientia from AMDZone said...

Actually, it would only take Intel about 9 months to put a memory controller on the die (and they would have already done this). Intel already makes these on its northbridge chips so it is quite familiar with them.

The problem is that an onboard memory controller is useless without a point to point bus like HT. Intel's solution to this is CSI but Intel started way too late in trying to establish a hardware technology base for CSI. CSI is essentially an upgrade of PCI-e. The problem is that PCI-e is a star topology similar to what is used with 100base-T ethernet. This works well with multiple cards but is not a good solution for interprocessor communication because it requires a hub for bus buffering, retry, and forwarding. Now you could technically add this function to the northbridge but it would double your latency. To have lower latency you need something a bit different from PCI-e. And, Intel did not start pushing a different version of PCI-e until very recently with Geneseo. And, Geneseo won't be available until 2008. Intel needs an onboard memory controller, a different cache protocol (like MOESI), CSI, and a new socket. That is why it will be 2009.

8:43 AM, January 05, 2007  
Blogger Scientia from AMDZone said...

As far as the added latency goes this appears to be a change that AMD put in awhile ago. Apparently they thought that they might need to go up to 2MB's per core on FX and 8xxx K8. However, the crunch in 2006 caused them to reduce cache size and now it isn't needed. There is no conspiracy or ulterior motive; sometimes you just can't plan ahead that well.

8:46 AM, January 05, 2007  

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