Wednesday, January 25, 2006

AMD's current generation is more advanced than INTEL's next generation Conroe

We all know this already, INTEL is 5 years behind. But here is more detailed look at the core. The problems with INTEL's Conroe/Merom are discussed here.

Compared to Nebojsa Novakovic's speculations, Josh Walrath has offered us true insights.

Nebojsa Novakovic failed to mention the most fundamental design choice in both Alpha EV7 and Opteron: the embedded memory controller. The Alpha designers had long realzied that memory latency and bandwidth were the foremost limiting factors for system performance (there was a seminal paper which I wasn't able to find a link). Once you choose the route of embedded memory controller, something like ccHT is a must have in order to connect multiple memory controllers together, cache coherently. Nebojsa Novakovic also claimed that INTEL is using HyperTransport in their chipsets, which is probably misunderstanding of the basics. INTEL is not a member of the HyperTransport consortium, which AMD has a lot of control. Furthermore, AMD has only opened up HyperTransport for I/O, it has not yet licensed the true crown jewel, the ccHT to anyone yet, though it's planning on doing it.

All modern CPUs, such as Opteron, Power5, UltraSparc T1 and Alpha EV7 have embedded memory controller(s). The T1 has four memory controllers, and I believe Socket F opteron will have at least two memory controllers.

Oudated designs such as Itanium, Xeon and Conroe use shared FSB.

Nebojsa Novakovic suggests that INTEL should adopt HyperTransport since CSI is delayed until 2009. But things are not so simple. Non coherent HyperTransport is an open standard. But AMD kept to itself the ccHT protocol for inter processor communications. ccHT is what INTEL needs, and there is no way AMD give it away for free.

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