Saturday, December 03, 2005

INTEL enterprise roadmap hopeless

Tomshardware published an INTEL roadmap which goes as far as 2008. Judging from the information presented, INTEL probably lags even more behind AMD in CPU architecture and multi-core design. When we look at modern CPU designs such as AMD Opteron, Alpha EV7 and Sun UltraSparc T1, they all have one thing in common, they have on die memory controller to reduce memory latency. The UltraSparc T1 has 4 memory controllers, and we expect the socket F Opterons to have at least 2 memory controllers. Opteron and UltraSparc T1 are true multi-core designs as multiple CPU cores reside on a single piece of silicon connected with internal multi-GHZ links. However, in INTEL's dual core design, the two cores don't know they are sitting next to each other on the same die, they go out to the FSB to communicate, which is a very primitive design. The next generations of INTEL server CPUs won't even pretend they are multi-core, instead they will be multi-die--basically INTEL will pack multiple CPU dies into the same package and call it multi-core, these cores don't talk to each other directly any way.

The INTEL Dempsey (Netburst/Xeon) will be dual die with 4MB cache, expected release date is mid-2006.

The INTEL Whitefield will be quad-core with 8 to 16 MB cache and will be released in 2008.

The INTEL Hapertown will be a multi-die CPU with 8 cores and will also be released in 2008.

INTEL's inefficient design requires at least 2 to 4 MB of cache for each CPU core, the doubling of cache negates any gain INTEL made by shrinking to 65nm. In contrast, AMD's Opteron only needs 1MB. We see almost linear performance scaling in 8 core Opteron systems.


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