The AMD64 Rev G Mystery
Looking at AMD's presentation in its June 1, 2006 analyst meeting, there is an interesting slide about Rev G production . Pay attention to the wafer picture on the right (the words say "High-performance, power efficient 65nm AMD64 processors on production 300mm wafer"). Those were definitely Rev G dies. One guy has written this analysis on the Rev G. Basically, the conjecture was that the extra circuits include one additional complex decoder, an OOO Load/Store buffer and OOO read/Write buffer. However, there is also this large block below the L2 cache, which is quite a mystery.
AMD spent a lot of time talking about Rev H (K8L) during the anaylst meeting, but it gave virtually no information on the capabilities of the coming 65nm Rev G. A side by side comparison of the original Opteron and Rev G is here.
I think AMD may have delayed the Rev F Opteron to pull in Rev G.
If AMD pulls out a Rev G on July 23, 2006 to frag Conroe, don't be surprised.
However, if AMD does it, you can write off Intel from history in four quarters instead of seven. Intel will continue to exist for a while, like DEC did. Then it will be gone with the wind.
posted by Sharikou, Ph. D. @ 6/13/2006 05:48:00 PM
44 Comments:
One of the rumors is Z-RAM L3. Do you have a "ball park guesstimate" of how long would it take for AMD to integrate zram L3 caches?
hahahaha...
i remembered when Conroe came out, AMD fanboys are like.. wait for Rev F. Rev F is going to beat Conroe once and for all!
and now... they're like.. wait for Rev G. Rev G is going to crush Conroe!
so how about, wait for Rev Z. Rev Z is going to beat Conroe for sure!!
"so how about, wait for Rev Z. Rev Z is going to beat Conroe for sure!!"
Rev. E already beats Conroe, F and G are just the icing on the cake fanboy.
"Rev. E already beats Conroe, F and G are just the icing on the cake fanboy."
proof?
just in case you're not sure, proof means "confirmed by experiment", not "because adding this will increase by 15%, so theoretically it should outperform something".
keep trolling!
I remember the time when conroe isn't out yet.
...proof means "confirmed by experiment", ...
And... in this case, it's pushing some buttons Intel setup.
So you line up 30 very willing nerds like you (all jumpity joyful like it's a 2nd X-mas), and write down whatever results that "button" pushing experiment showed on the screen...
Call it a pre-view , be wiped around the net and lose credibility, all the while... being a pawn of Intel in their marketing game.
If you are referring to this http://129.15.202.185/athlon_rev_g/wtf_mates.html
Judging and guessing architectures from a die pix is considered HIGHLY UNRELIABLE. Its like trying to guess building names, height and structure from a satelite pix. That "rev. G" die looks more like a (non-working) prototype! If they do have a working silicon, wouldn't have AMD reps shown (and demo) it to the public (and to stir up investor confidence)?
Better (and more reliable) information here: http://pc.watch.impress.co.jp/docs/2006/0531/kaigai273.htm
65nm, where art thou?
"Call it a pre-view , be wiped around the net and lose credibility, all the while... being a pawn of Intel in their marketing game. "
What kind of preview can you offer then? Or there's no need for such things because there's nobody you can trust in the world??
65nm, where art thou?
http://www.hardocp.com/images/news/1149260964gKMXB1SZgn_1_1_l.jpg
http://www.hardocp.com/images/news/1149260964gKMXB1SZgn_1_2_l.jpg
...proof means "confirmed by experiment", ...
http://www.tweaktown.com/imagebank/computex06_conroebenching_03.gif
http://www.tweaktown.com/imagebank/computex06_conroebenching_09.gif
Conroe Athlon
3GHz 2.8GHz
SATA ATA/133
2Go PC2-8500 1Go PC2-8000
According to http://www.hardocp.com/news.html?news=MTkyNTgsLCxobmV3cywsLDE= (that link from "Conroe Athlon") quotes "While I was writing this, Cray began to talk about how they could plug in specialized FPGAs DIRECTLY into an AMD Opteron socket, allowing for seamless communication between the two technologies." What? Opterons?!!
Another quote "I was fortunate enough to be able to ask specifically if we will see this technology integrated into AMD’s 4x4 enthusiast platform and the AM2 architecture. I was told that while there were no specific plans for HTX add-in co-processors in AM2 architecture at this time, there is the definite possibility should consumer demand crop up.".. contradicting statements, ain't it?
Benches please.. CPU-Z screenshots please.. Thermal and TDP numbers unannounced either. I don't see Windows running there. Looking at the screenshot, looks like this silicon is rushed out of prototyping (or production).
I don’t understand people expecting so much from AMD as from Intel since their products are already good.
However Conroe is more strange to me, since Intel will be releasing what is supposed to be the "Core" architecture, when as far as I know Core duo is already on laptops many months ago and I didn’t see too much Whooo about it.
Just because its going desktop and server is for applaud, since P4 is not too good.
Besides what does Conroe and Woodcrest bring NEW into the market? What technology advances are there?
More performance, good. And...
http://www.amd.com/us-en/assets/content_type/DownloadableAssets/MPF_Hammer_Presentation.PDF
Does Conroe look good as this 5 year old presentation?
Hi from Italy.
Intel, with Conroe, has maybe (note: maybe) made the best single thread, single core, 32bit processor in the x86 arena.
But applications, OSes and programs are requiring more and more as time passes multi-thread, multi-core and 64bit processors.
Intel may have done a good job for a product market will care not as time goes by.
And it seems to me that it has little to zero future in terms of "platform" longevity (i.e. chipset, socket and so on).
...proof means "confirmed by experiment", ...
http://www.tweaktown.com/imagebank/computex06_conroebenching_03.gif
http://www.tweaktown.com/imagebank/computex06_con
you must be kidding me, the first link is the only benchmarks out of so many that the AMD won. The 2nd link and the rest Intel Conroe is thrashing AMD's. I guessed you have intepreted the 2nd one as the lowest FPS win :). Please do not pick on choose the data that you wanna see.
"What kind of preview can you offer then? Or there's no need for such things because there's nobody you can trust in the world?? "
I trust a lot of people... just not Intel since I've seen their marketing techniques for years.
A "preview" of a future product NOT even out yet, setup by Intel that you can touch/modify/analyze, compared to a current offering by AMD (setup by Intel) in a biased environment... is not a true comparison to me.
--> This is like Coke running a taste compared to Pepsi for a product they're coming out with in 6months. (with professional taste testers of course)
100 other sites, who pushed the same buttons, all with the same "biased" setup is called Marketing Hype (surprising all came out with a review on June 4th as Intel mandated). It's Marketing 101, and Intel is the best at it.
Not bashing on Conroe, but let's see some TRUE independent review when they are available (meaning you and I can go buy it), and see how it really fares.
People are running around kicking & screaming as if Conroe is out, and price is all set?!?! Do you know how their yields are? How do you know what their prices will be?
Only time will tell, and in the meantime, I'll enjoy my Athlon64x2 4800+ that's available NOW, and a PC that I'm actually using NOW.
Either way, it's great for us consumers, but bad for stockholders. :)
Rev G Info:
http://www.aceshardware.com/forums/read_post.jsp?id=120058172&forumid=1
in a few month i will go xeon 5100. not because of the processor. i will go intel, because their motherboards and chipsets are the best on the market.
the lack of a decent chipset for amds great processors is the largest weakness of the athlon\opteron platform!
Eddie said...
One of the rumors is Z-RAM L3. Do you have a "ball park guesstimate" of how long would it take for AMD to integrate zram L3 caches?
Dave says:
I think you may be right...
1) AMD liscensed ZRAM already.
2) ZRAM uses 1/5 the size of L2 cache, at about the same speed.
please see:
http://en.wikipedia.org/wiki/ZRAM
http://www.tgdaily.com/2006/01/24/amd_licenses_zram/
So that would mean that the blocks sharikou finds mysterious would be:
4MB of ZRAM L3 cache!!!!
This would be huge, as the combination of 1MB of L2 and 4MB of L3 would be a strong answer to Conroe's 4MB cache. I think it would certainly negate any memory advantage we have seen in Conroe's SuperPI tests or others that task primarily to the cache. What remains is what the tests would reveal about hypertransport from CPU to L1 to L2 to L3 to DDR-2. If past design reviews are used as a baseline, the clear advantage goes to AMD hypertransport over Intel FSB! This is even more important when you consider the upcoming 4x4 designs - 90 nm ZRAM switches at about 3ns, and 65 nm would be faster (2ns?) due to shortened leads - so that could mean a very high speed data transfer from one AM2 socket L3 to another. Ponder the possibilities of high speed memory transfer as a better solution than cranking up clock speed (and wattage).
I remember reading somewhere that ZRAM cache is slower than SRAM, what impact will that have on performance improvement expected from the additional cache?
As I do not understand the dfferences betwen L2 and L3 cache could someone comment on the difference between the two and what the performance difference is between the two in a deskktop/mobile environment, if any?
"Can anyone show me a benchmark where the Athlon 64 clearly beats a Core 2 Duo at 2.4Ghz. I doubt that."
I have to doubt you have even a brain. http://www.tweaktown.com/articles/914/benchmarking_intel_conroe_core_2_x6800_e6700_and_e6600/index.html - There's a 2.6GHz w/ 512KB Cache nearly beating a 2.95GHz Conroe...and it's also showing a 2.4 right on par with a 2.95 conroe in gaming tests....can somebody say "Conroe sux and its cache is only good thing"?
Fanboy = Just Got 0WN3D
Dave also says:
Refer to the coverage on analyst day:
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2768&p=3
AMD shared some new architecture directions which rely on L3 cache as an important part of the K8L:
"On a very slightly lower level architecture side, we have a slide showing the overview of AMD's next server class processor with 4 cores based on K8L. Features include a shared L3 cache, "enhanced IPC" cores, OoO (Out of Order) loads, wider data paths, HT-3 (the third version of HyperTransport), and support for DDR2 (and DDR3 or FBDIMMS in the future). Details on some of these enhancements were way too light, especially on the IPC (Instructions Per Clock) front.
Cache enhancements include the capability to support 2x128-bit loads per cycle from the 64k L1 cache (which is half the size of the K8 L1 cache), and a shared L3 cache which will scale up from its introduction at 2MB. The shared L3 cache will help with features like node interleaving on multiprocessor systems as well as multithreaded apps which make use of shared data. We are still waiting for more detailed data on the cache architecture. It isn't clear whether the caches are all exclusive, and we would like to know more about associativity as well." It would seem that a L3 cache based on ZRAM is part of the server roadmap, and doesn't take much of a leap to infer that such a cache would be part of Rev. G. Also I find it typical that AMD tries to do Intel "one better". When Intel introduces some tech to their chips to equal or better AMD, AMD has reliably countered with twice the bits (32 v 64), better memory tech or new revolutions in architecture. ZRAM would follow this paradigm.
Anonymous said...
I remember reading somewhere that ZRAM cache is slower than SRAM, what impact will that have on performance improvement expected from the additional cache?
As I do not understand the dfferences betwen L2 and L3 cache could someone comment on the difference between the two and what the performance difference is between the two in a deskktop/mobile environment, if any?
Dave says:
Read these:
http://www.amdzone.com/modules.php?op=modload&name=News&file=article&sid=4767&mode=thread&order=0&thold=0
http://www.innovativesilicon.com/en/pdf/z-ram.pdf
What I find very interesting is the whitepaper comment about process shrink: "Z-RAM test chips fabricated in a 90nm SOI process have demonstrated read/write speeds faster than 3ns, and performance will scale with future process shrinks." and "five times denser than six transistor SRAM." This means AMD will be able to integrate huge (4MB, 8 MB, 16 MB, 32 MB) L3 (and soon L2) caches on the die and PER CORE! Imagine a Rev G AMD64 6000+ X2 w/ 1MB L2 and 8MB L3 per core! This probably could be introduced with the new 65nm parts. Even a conservative timeline could pull such parts into production this year. It makes me understand why AMD folks wouldn't be too concerned with Intel's Conroe, because they don't have to pre-announce that a killer memory tech is on the way.
"can somebody say Conroe sux and its cache is only good thing"...
Mad Mod Mike, I had posted this on your blog a day or two ago, and now it seems that "almost wins" is good enough to link to it. You have stated before that Conroe is better in gaming.
Cache or not, we dont know yet, as there have been no benchmarks showing the performance of a 2Mb Core 2. Intel may be hiding these numbers, but we simply don't know.
Doom 3 benchmarks...
X6800 has a almost a 30% advantage over the FX62, but only a 8% advantage over the E6600...
Quake 4 benchmarks...
X6800 has a 10% advantage over the FX62, but only a 0.87% over the E6600...
F.E.A.R. benchmarks...
X6800 has a 2% advantage over the E6600 and a 6% advantage over the FX62, not very impresive...
As I pointed out the FX62 only has a 4% advantage over the Intel 631 in the F.E.A.R. benchmark, so there may infact be more room for improvement, since it was concluded that their must be a bad setup or test.
As I do not understand the dfferences betwen L2 and L3 cache could someone comment on the difference between the two and what the performance difference is between the two in a deskktop/mobile environment, if any?
Dave says:
Here is a detailed article on cache and cache operations:
http://en.wikipedia.org/wiki/CPU_cache
In general, and IMHO, it is nice to have a fast, energy efficient processor. But, It also matters how fast the computer can move data from the storage (hard disk) to the processor. You can usually see this when the HD light keeps blinking on your PC. You may also notice that computers are quite slow when they are moving data like this.
Going forward, the most important advances (IMHO) will come from improving this pathway of the PC. Some have noticed that MS has specified a "hybrid drive" for Vista Premium. This is a hard drive that includes SRAM as part of the Hard Drive, enabling a faster movement of start up or operating files from the hard drive. The next higher stage of the path is system memeory, which has been addressed by the introduction of DDR-2 and DDR-3. Since the CPU already has a small fast local memory (L1) the remaining bottleneck in memory throughput will become L2 and L3 Cache. These will both be vastly improved by ZRAM tech. It also should be mentioned that these memories are hopefully sized to improve their effectiveness. For instance, the L3 shoulb be at least 4 times the size of the L2, which should be 4 times the size of the L1. It helps even more that the bigger the lower caches are made(6x, 8x 10x), causing less movement of data to be moved from disk to sytem memory to L3 to L2 to L1. You may notice that server CPU's have huge L2 and L3 caches. This is due to promote the recurrent possibility that the data needed/requested is still being stored in some part of the cache before it is written over by some other requested data. I personally love the idea of huge caches on the CPU, with new Solid State Hard Disk Tech. It will improve the speed of the entire computing system, not just the specific jobs the processor does, like run SuperPI. Imagine a day you won't sit and watch the blinking hard drive light for 45 seconds while you wait for your computer to boot, load your favorite game or spreadsheet application to load!
To last poster - Thanks (although first link doesn't seem to work).
My concern is speed of ZRAM - you mention raw speed of ZRAM and WP mentions it is faster than DRAM but how does it compare to L2/L3 conventional SRAM speed?
I've heard others argue that because of HT, AMD gets less benefit from additional cache, any estimates on what performance this might mean to an AMD chip?
Mark-Eric Jones, the CEO of Innovative Sillicons (company that developed z-ram) is quoted, that it takes usually 2 years, between the contract signing for z-ram and the first products with the new technology.
analysts predict that it's very likely that amd will wait until they move to 45nm process (in 2008) before they introduce z-ram ...
I find it hilarious that people on this site or any other fanboy site think that it takes a matter of weeks or months to design, implement, and integrate anything into a processor. The fact is, it takes months and months of designing, debugging, and testing to get things right. It's not as easy as attaching another 2 megabytes of cache onto the processor; even something as simple as cache takes time to implement. So if you guys seriously think that AMD announce some sort of miracle processor right after Conroe is officially released, you guys are kidding yourself.
It has an odd appearance for a simple reason: an image was applied over the die photo to provide a better background for the overlying text.
I suggest you look at the wafer shot with a lot of Rev G dies. AMD carefully blurred the area below the L2 on all these dies.
Dave says:
1)Broken link, try this one:
http://www.tgdaily.com/2006/01/24/amd_licenses_zram/
2)Mark-Eric Jones, the CEO of Innovative Sillicons (company that developed z-ram) is quoted, that it takes usually 2 years, between the contract signing for z-ram and the first products with the new technology.":
Apparently, they finished design in mid-2005, signed contract w/AMD in beginning of 2006, and produced silicon in Feb. 2006. Since their R&D is in Switzerland, what are the odds that SOI silicon was
produced in the foundry of Dresden? Since AMD is using SOI, I find it likely, and a collaborative effort between both. I also note the quote above, and let you parse the term "usually" in this context. My memory says most CEOs make such statements with the term "can". The interesting choice of his wording suggests something will come sooner. Hmmmm.
"My concern is speed of ZRAM - you mention raw speed of ZRAM and WP mentions it is faster than DRAM but how does it compare to L2/L3 conventional SRAM speed?
I've heard others argue that because of HT, AMD gets less benefit from additional cache, any estimates on what performance this might mean to an AMD chip?"
This is a complex question. It is first important to note that the length of the connection from processor to controller to cache matters greatly. What I have found is that SRAM L3 currently runs at 4 ns, L2 is at 3ns, and L1 next to the processer at nearly 2ns. If you look at specs for SRAM discrete chips you find times around 8-10ns. In short, the bigger the block, the slower the switch. The inherent delay from lead length and capacitance is due to the nature of 6T (transistor) SRAM, you get speed at the price of space and energy. Fast, close L1 is essential, but you get tradeoffs as the SRAM is moved farther away on the CPU die. So, other techs would be a better choice for 65nm. In short, 1 T caches on the die would be a better choice. 1 T SRAM seems to be the next stop for intel on their dies, but some problems with accuracy have seemed to arise. Time will tell for intel, but they seem perfectly willing to load the die with 6 T storage of 4MB to speed Conroe. For AMD, they have moved to SOI, which allows other cache techs to be used, specifically quicker FET designs. The time for the input signal transition can be significantly less, due to less complexity, inherent construction, no included capacitance, and the inherent smaller footprint of the bank of FETS. This FET design also has more linear increases in speed with die reductions, whereas 6T starts to have more noise problems with scaling down. The switch speeds of the ZRAM FETs are falling below 3ns on 65nm, which is better than SRAM can do! It margin on L2 cache seems to be better, but at a smaller margin. An extra benefit seems to be a reliability of data integrity within the cache, by a factor of 5x. As for benefit of larger caches, I think Sharikou could answer best, but I would think that the increase in size versus memory benefit is not as linear as it is for Intel. Dr. Sharikou: Please comment.
I wouldn't count on Z-RAM. If it works, Z-RAM will be great. But, so far we haven't seen it in action anywhere.
Dave says:
Sharikou, Please look at this interview,
http://www.geek.com/news/geeknews/2006Mar/bch20060330035564.htm
,especially the evasive parts about where they are using foundries to produce samples, and the quote from Craig Sander, the VP of Technology Development at AMD, "is that by using Z-RAM as additional cache memory within the processor, they will save on I/O power in the processor." I believe the parse of "they will save" is a definitive, the speculation is now on when! I'm also not the only one expecting this tech, see:
http://www.geek.com/news/geeknews/2006Jan/bch20060216034806.htm
http://www.geek.com/news/geeknews/2006Jan/bch20060214034760.htm
http://www.geek.com/news/geeknews/2006Mar/bch20060331035588.htm
I also think you're right about not counting on ZRAM. I could well be that the masking of all the Rev. G dies conceal an innovation that is still being tested, and maybe/will only be revealed at a later time. Time is still a good question. It would be a great counter to Conroe, but relies on the ability to bring it to the production in record time. Realistically, if you were the CEO and had a liscense to manufacture it, wouldn't you do everything to get it out there to kill Conroe, Merom, and Woodcrest?
That Rev G die could have 1MB L2 and 3MB L3 in Z-RAM. Let's wait and see. I really think AMD will bring out something on July 23, 2006 to frag Conroe.
"That Rev G die could have 1MB L2 and 3MB L3 in Z-RAM. Let's wait and see. I really think AMD will bring out something on July 23, 2006 to frag Conroe."
wow...and these are the same people who whinned, "Conroe is a future product! it cannot be compared to a currrent product!!"
Read on.. "Update: AMD To Ditch Initial AM2 2x1MB Cache Desktop CPUs" at http://www.dailytech.com/article.aspx?newsid=2858
And "The Tech Report - AMD confirms X2 chips with 1MB L2 cache are toast" at http://techreport.com/onearticle.x/10175
Wow, REDUCED CACHE! From 1MB back to 512KB!
i will go intel, because their motherboards and chipsets are the best on the market
Why they are better than those of NVidia or ATI?
Anybody knows the size of Conroe XE? How many of them can be placed per wafer?
So why isn't AMD touting their new improved supadupa chips? Simply because they try to avoid the Osborne effect. Intel indeed does harm itself by making people waiting the 'new king'. Honestly, if you are a Intel fanboy, admit that youre waiting and not buying anything from Intel. And lastly, when Conroe shows itself in buyable form, where do you think AMD really is? I think that Intel is finally done a Superpi processor for aiding that everlasting war between fanboys. Its all about benchmarks.
"Anybody knows the size of Conroe XE? How many of them can be placed per wafer? "
Don't know exact size... but with 4MB L2 Cache PER CORE... that's one gigantic die regardless it is 65nm or 45nm.
Defects are random when producing wafers, and the bigger the die, the lower the yield. THIS IS FACT!
Expect to see an influx of 2MB L2 Conroes... They'll just block off 1/2 the cache that doesn't yield and sell it cheaper.
they are going to have a world of a time getting yields:
1) While ramping up 45nm
2) HUGE L2 Cache
3) Gigantic Dies!!
Sharikou, it's chicagraf0/todospara1 here my blog at http://chicagrafo.blogspot.com
I asked you about ZRam L3 because although it isn't in action anywhere, as you pointed out, it may be that AMD had prior experience with that idea tahnks to their own indie developments.
There is the rumor that AMD only licensed ZRam from Innovative Silicon to clear the path for their own ZRam technology, thus they may be very advanced in that direction, closer to market than expected.
It is just speculation, but I would like to know your opinion about this possibility
In the digitimes interview, the Innovative Silicon guy hinted that AMD is using ZRAM for an additional stage of cache to save I/O power. I won't surprised if Rev G has ZRAM in it. Again, if it does have ZRAM, you can write Intel off the book even quicker. There is no way Intel can switch to SOI in one year. One year is all AMD needed to kill off Intel. You have to pay great attention to AMD's capacity graph.
Thank u 4 ur reply.
Thus, ZRam is a possibility 4 u although you wouldn't count on it, right?
"they are going to have a world of a time getting yields:
1) While ramping up 45nm
2) HUGE L2 Cache
3) Gigantic Dies!!"
This is just speculation, but 45nm is not until 2008, right?
Isn't it possible that 45nm will have the internal memory controller they have been working on?
A quote from EETimes...
"Intel plans to embed a memory controller and to use a common high-speed serial interconnect as the processor bus for its Itanium and Xeon server processors starting in 2007"
Also this link...
http://www.theregister.co.uk/2005/12/12/intel_csi_low/
This may be coincidence, but the timing seems about right.
Thanks.
Such portentious sentiments! Ooooh - 4 quarters! Intel History!
You are, and always have been, an idiot and a scumbag, and your idiotic prognostications nothing but the blatherings of an angry, deluded fool, jackass.
Intel packs cache 2x denser than AMD and Conroe is only 140mm^2.
About the die photo , the "mystery area " is nothind more than empty space , as said by an AMD employee.
Too bad so many think AMD is hiding its wonder weapons...when there are none.
Dave says:
I'm still seeing purple spots!
Dr. S, do you speak japanese?
Follow the thread here:
http://babelfish.altavista.com/bab
elfish/urltrurl?lp=ja_en&trurl=htt
p%3a%2f%2fpc.watch.impress.co.jp
%2fdocs%2f2006%2f0531
%2fkaigai273.htm
Under the chapter,"With the multiple core cash class is deepened" it talks about a certain
revision CPU receiving an increased L3 cache, the damn thing is partly in japanese, but I can make out that Phil Hester quietly is talking of "variation" being introduced in the Rev F CPUs. We are starting to see smaller L2 caches, can it be they are readying
release of L3 on Rev F? Please glean some more out of this article, it seems this reporter actually had sat with Meyer and Hester on June 1st. They seem to have covered a number of coming improvements, but I can't read the important part. Please help!
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