Intel Tulsa/Truland Xeon MP profile
Intel announced today that it will pull Tulsa's 4Q06 launch into 3Q06. Tulsa, Intel's codename for:
Imagine a DELL PowerEdge 6850 with 4 such suckers. 600 watt typical heat from the processors alone. Total 8 cores, 16 threads, sharing 667/800 MHZ bus. Each core gets an average of less than 100MHZ FSB bandwidth, each thread gets less than 50MHZ bus bandwidth, or 0.4GB/s, less than that of a 80486.
You interested in this big piece of silicon? It's dirt cheap.
But be prepared to pay 600 * 24 /1000 *365 * 0.18 = $946 a year for electricity. No, double that for cooling cost. If Google used Tulsa, it would need 30 mega watt of power.
posted by Sharikou, Ph. D. @ 6/09/2006 05:35:00 PM
9 Comments:
I need one of those for the harsh winters in Alaska.
I have a question about Tulsa, it has 16MB of Shared L3 Cache and 1MB L2 Cache per core, but how do the cores communicate? Do they use the same as Core 2 Duo or do they use the FSB?
I would also assume this has 2 FSB'S, but if it doesn't, than this is just disgusting. 150w TDP = Bye Bye Intel in Blades.
Why 3rd quarter and not now?
"Why 3rd quarter and not now?" - '16MB Shared L3 Cache'
Dare I say....yields? o.O
It should be interesting to see what the 16MB Shared L3 does for performance.
tulsa seems still netburst based, what do you expect?
With 16MB of L3 cache I really don't see how this product can be produced with any reasonable yields!
How do they do it? How does Intel produce all of these (large) prcessors with only 3 65nm FABS?
And you say its "dirt cheap"!
More of these babys will be sold in homes then sold as low-end servers.
They should perform reasonably though with 16MB of cache.
First of all, a Tulsa system would generally be 4 sockets over 2 FSBs in other words 8 cores over 2 800MHz FSBs. Therefore, it's very clear that each core would have 200MHz of bandwidth available, not 100MHz as you exagerrate. Also, more bandwidth is actually available than previous from Paxville MP since the shared L3 cache means that you only have to deal with cache coherency for 4 cores not 8. Since coherency traffic increases proportion to the square of the number of cores, this is a very significant reduction.
Now you may complain about cache trashing, but it has yet to be proven to happen on the Core architecture. Certainly if it has similar dynamiz allocation logic as Core to prevent a single core from monopolizing space unfairly thrashing is unlikely. I don't really see a single core being able to take up the whole 16MB L3 cache anyways. Even if it were to happen, the second core still has it's 1MB L2 cache which is as big as Opteron's. If AMD is used separate L2 caches and intelligent L3 cache logic as their justification for avoiding cache trashing, I don't see how this wouldn't apply to Tulsa. Unless AMD's reasoning is flawed.
Intel is not going to produce it for money, they, as usual, try to start the production just to say "we are the first who developped 4-cores chip".
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