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Intel has no problem pumping its chips to gullible journalists and script kiddies. But Tom Yager at infoworld is wondering why Intel pulled a no-show at the Spring Processor Forum, which chip designers use to demo their know-how. Actually, Intel is playing hide-and-seek with script kiddies too, the latter are just too overjoyed by the attention Intel giveth them.
posted by Sharikou, Ph. D. @ 5/31/2006 10:48:00 AM
19 Comments:
Intel knows that AMD is ahead of them and will be forever, the problem is that if Intel can't brainwash the people or control the PC's or make special ES's, they won't attent.
Intel knew any attempt at fraud would be exposed there so why show up to a party where you'll most certainly get trounced?
Link
I've put together an interesting composit of the 2 companies and their futures, it's worth a gander and it plays into Intel's unlawful behavior and a reason for Intel's shyness towards provability.
if intel is being "shy" on the performance of conroe, then explain to us why intel has not sent out a flurry of cease and desist orders to various people on the web that are benchmarking processors and putting the (great) results on the web? the NDA on conroe (and presumably woodcrest and merom) is not up until june 4. i'm sure those people do not have NDA's but they are releasing info on an unreleased product...
This is part of Intel's marketing. Intel will not care about any NDA's or of such if it is good publicity. Intel most likely gave out the best processors they could, and on doubt, those are not the chips people can buy.
What I want to see benchmarked is a 2MB Cache Conroe, so everybody can see the truth about the performance. Conroe is a good performer, but not because of its architecture, but only, and I repeat, ONLY because of 4MB Cache.
People say if it performs, who cares...well...you'll lose out eventually, when you have to upgrade your entire platform for future-proofing, whereas AMD and its unified platforms offers upgrades from DDR2, DDR3, and FB-DIMM's, and etc. w/o requiring huge upgrades. I bet every Conroe upgrade will require a new Intel chipset mobo.
I wonder how much of the Woodcrest (aka Bensley) performance is due to its use of FB-DIMM, and how much more favorable is FB-DIMM compared to DDR2, performance-wise?
From this Tech Report page it seems FB-DIMM has over 20GB/s bandwidth, twice as much as dual channel DDR2-667.
I know FB-DIMM is more expensive, more power-hungry, and probably unstable at this point, and these could contribute to Woodcrest's lower TPC and less stability. I also know that Woodcrest with FB-DIMM performs very (>30%) favorable, compared to Opteron with DDR/2, on some standard server benchmarks.
I have heard that Intel compilers deliberately switch off certain features of AMD processors so that they have a poor score.You will notice that certain benchmarks used an Intel C++ compiler for Opetron systems.
FB-DIMM's have as much as Six-Channels per Controller, and current Bensley systems use 4-Channels. FB-DIMM's at DDR2-667 provide 21GB/s, but Dual 1.33GHz FSB's can handle 21GB/s max. If you compared Woodcrest in 4P vs. a DDR1 Opty 4P, they'd have roughley the same bandwidth with the Opteron using DDR400 (8-Channels compared to 4 though).
The Opteron's w/ DDR2 can have 21GB/s Per CPU, and in a 4P system, that's 84GB/s Memory Bandwidth and 42GB/s in 2P, vs. 21GB/s w/ Woodcrest for all levels. I wouldn't be surprised if we saw Six-Channel on Opterons per CPU and saw 30GB/s per CPU Bandwidth, which would put Woodcrest to shame in an instant.
If you compared Woodcrest in 4P vs. a DDR1 Opty 4P
Woodcrest/Bensley is an imitation of Athlon MP's dual independent bus, that technology is only good for 2P. There will be no 4P for Woodcrest.
There will be no 4P for Woodcrest.
But if Intel has had 2 processors on a single bus, what makes you think that they won't make a 4P Xeon platform with only two FSBs? The performance would be pathetic (such as in a single shared bus architecture), but it could be done.
I forget the article I read, but I believe it mentioned that for 4P and up, Intel was still going to rely on Netburst-Based Xeon's all the way up to 8P, so you can have 16 Processors (8 Dual-Core) sharing 2 FSB's...lol, that is truly hillarious.
I forget the article I read, but I believe it mentioned that for 4P and up, Intel was still going to rely on Netburst-Based Xeon's all the way up to 8P, so you can have 16 Processors (8 Dual-Core) sharing 2 FSB's...lol, that is truly hillarious.
No, you'll have 4 FSBs since each 4S node has 2 FSBs. And these systems from IBM and Unisys can scale to 32S and perform quite well. Unlike Opteron past 4S.
And these systems from IBM and Unisys can scale to 32S and perform quite well.
You mean this?
4P Opteron trounces 16P Xeon
*quote*
What I want to see benchmarked is a 2MB Cache Conroe, so everybody can see the truth about the performance. Conroe is a good performer, but not because of its architecture, but only, and I repeat, ONLY because of 4MB Cache.*end quote*
Why do you think that? The current Pentium Ds for example... have 4mb of L2 cache (2mb for each core), and that's resulted only in a minor increase in performance over the old 90nm Pentium Ds that had 2mb cache (1mb per core). They still get soundly beaten by AMD's Athlon 64 X2 procesors - even those that have a seemingly mediocre 1mb of l2 cache (512k per core)! That should be proof that just adding cache doesn't do that much to performance.
"No, you'll have 4 FSBs since each 4S node has 2 FSBs. And these systems from IBM and Unisys can scale to 32S and perform quite well. Unlike Opteron past 4S."
Incorrect, the northbridge ONLY allows up to 2 FSB's, regardless of the processors. On Woodcrest, each CORE has 1 FSB, so in a 1P system, there is 2 FSB's. In a 2P system, each PROCESSORS (both cores) share 1 FSB and the other processor (other 2 cores) share the 2nd. There can never be more than 2 FSB's in any Bensley system.
Incorrect, the northbridge ONLY allows u to 2 FSB's, regardless of the processors. On Woodcrest, each CORE has 1 FSB, so in a 1P system, there is 2 FSB's. In a 2P system, each PROCESSORS (both cores) share 1 FSB and the other processor (other 2 cores) share the 2nd. There can never be more than 2 FSB's in any Bensley system.
That has no relevance, since Bensley isn't used in Xeon MP systems.
"That has no relevance, since Bensley isn't used in Xeon MP systems."
I am talking about the amount of FSB's in Bensley, so I believe it has relevance. Xeon MP systems are a joke, 4 or 8 Processors on a Single 800MHz FSB is so funny it hurts, even if Intel uses Bensley for 4P+, it still has a big issue with the FSB.
Once Intel decides to use CSI (Reverse-Engineered HyperTransport I bet) it will run into another problem: latencies. HyperTransport is designed to provide low latencies and thus, work with low caches. If you put 4MB of L2 Cache on a 2P Opteron system w/ low timings, it could create additional latencies for the system.
If Intel can live to making CSI a reality, they'll have to do everything all over again with their caches just like they had to with the P4.
I am talking about the amount of FSB's in Bensley, so I believe it has relevance. Xeon MP systems are a joke, 4 or 8 Processors on a Single 800MHz FSB is so funny it hurts, even if Intel uses Bensley for 4P+, it still has a big issue with the FSB.
Except Xeon MP systems use 2 FSBs per 4S node, plus multiple scalability ports to directly connect nodes to each other, resulting in better scalability than Opteron can do gluelessly.
"Except Xeon MP systems use 2 FSBs per 4S node, plus multiple scalability ports to directly connect nodes to each other, resulting in better scalability than Opteron can do gluelessly."
Better scalability than Opteron....wow....some people are just too dumb for their own right...
the first favorable review about am2 boards I have seen on Internet is:
http://www.planetx64.com/index.php?option=com_content&task=view&id=215&Itemid=14
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