Tuesday, December 19, 2006

AMD capacity estimate again

The 65nm Brisbane die size is 126mm^2, using a geometry of 11.5 x 11.5 for the wafer program, we find a 300mm wafer can produce 492 dies.

At 18000 wspm at FAB36, quarterly die output is 18000*492*3 = 26.6 million.

At FAB30 (90nm), the die size is 183mm^2, with a geometry of 14 x 14, a 200mm wafer produces 137 dies. At 30000wspm, quarterly die output is 12.3 million.

Total AMD dual core die output 39 million per quarter.

Throwing in Chartred FAB 7 at a small number of 2 million, we get 41 million dies/quarter.

With a yield of 90% (mature yield, extremely low defect density), we get 37 million dual core CPUs per quarter, leaving a 20 million market for Intel.

Expect AMD to improve its 65nm transistor soon, and expect major clockspeed bump sometime next year.

PS: Some retards are wailing about this estimate. My suggestion, do your own math.

62 Comments:

Anonymous Anonymous said...

90% die yield are you high? You really don't know anything about manufacturing do you? I guess you must of worked in the marketing department at Intel....

12:43 PM, December 19, 2006  
Anonymous Anonymous said...

What is the die size for the core2duo chips? What was AMD's capacity before the switch over to 65nm? What percentage increase is it? THanks...

1:05 PM, December 19, 2006  
Blogger PENIX said...

But is this enough to finish off Intel once and for all?

1:36 PM, December 19, 2006  
Blogger Sharikou, Ph. D said...

But is this enough to finish off Intel once and for all?



It's all about market share, AMD's strategy is to expand market share and keep price down -- deny Intel the profit and force Intel to BK.

2:40 PM, December 19, 2006  
Anonymous Anonymous said...

It's all about market share, AMD's strategy is to expand market share and keep price down -- deny Intel the profit and force Intel to BK.
LOL, you got that backwards... I think that's what Intel is doing to AMD, pricing AMD out of the market.

2:57 PM, December 19, 2006  
Blogger Sharikou, Ph. D said...

I think that's what Intel is doing to AMD, pricing AMD out of the market.


AMD's average selling price never went above $100. So for AMD to sell any chip at $100 is a laugh to the bank. Intel, on the other hand, would BK if its ASP is at $100. That's the reality today. AMD keeps slashing prices as its capacity goes up. Intel suffers from both losing market share and lower unit price.

3:05 PM, December 19, 2006  
Blogger sharikouisallwaysright said...

Intel is going to cut C2D selling prices up to 40% in q2 2007.

4:45 PM, December 19, 2006  
Anonymous Anonymous said...

I'll try again:

1 Your die #'s/wafer are wrong. I bet you are using the geek.com wafer program and are using 2mm EE and 0 for the street? A few months ago you were at 690 potential die/wafer, now 492, soon to be...

You need some area to actually cut the die! And you also need to use at least 3mmEE for 300mm (depending on some of the tooling AMD chose it might even be 3.5 or 4mm). This alone is ~10% error in your #'s.

2. As another poster pointed out - your yield assumptions are wrong (and have no supporting data). This could be significant error in your overall #...

3. Your capacity situation is also wrong - when F36 is operating at 18K 65nm (mid next year), F30 will not be at full capacity as it will be starting to undergo conversion to 300mm/65nm.

Your capacity calculations are comical - looks like you are doing this with a HS education with no background in Si...you are using a very basic tool you found on the web and don't even understand how to set the 4 inputs that go into the model!

I don't suppose the position you were fired from at Intel had anything to do with manufacturing or capacity planning eh?

Just out of curiosity why is AMD only seeing 33% reduction in die size moving a product from 90nm to "65"nm - your past estimates in previous blogs was ~90mm2? Still waiting for a response on this one...

Well I'm off to home depot - I need 2 exact 6 foot boards. So I'll buy 1 piece that is exactly 12' and cut it in half - I'm sure the 2 pieces left over will still each be 6'...the sawdust on the floor I believe comes from the cutting blade not the actual wood!

4:59 PM, December 19, 2006  
Anonymous Anonymous said...

"AMD's average selling price never went above $100. So for AMD to sell any chip at $100 is a laugh to the bank. Intel, on the other hand, would BK if its ASP is at $100. That's the reality today. AMD keeps slashing prices as its capacity goes up. Intel suffers from both losing market share and lower unit price."

OK just because you say this doesn't mean it's true. Give us a link to where you pulled this number from.

6:57 PM, December 19, 2006  
Anonymous enumae said...

Below is total capcity +/- for FAB 30, FAB 36 and FAB 38.

FAB 30 90nm 200mm wafers

FAB 30 is scheduled to begin conversion in the middle of 2007, so the numbers show the production dropping to 50%, in regards to FAB 38 picking up the slack, just look below for that break down.

January = 30,000 wspm = 4,110,000
February = 30,000 wspm = 4,110,000
March = 30,000 wspm = 4,110,000
April = 30,000 wspm = 4,110,000
May = 30,000 wspm = 4,110,000
June = 30,000 wspm = 4,110,000
July = 15,000 wspm = 2,055,000
August = 12,500 wspm = 1,712,500
September = 10,000 wspm = 1,370,000
October = 7,500 wspm = 1,027,500
November = 5,000 wspm = 685,000
December = 2,500 wspm = 342,500

This gives you 24,660,000 (January - June) + 7,192,500 (July - December).

Thats 31,852,500 for the year from FAB 30 on the 90nm node.

FAB 36 65nm 300mm wafers and 90nm 300mm wafers

This section will get a little tricky, assume AMD is at 50% 65nm and 50% 90nm and we will scale for a full conversion by June, at which point all wspm will be 65nm.

At the same time wspm will increase up to 20,000 by the end of the year, so that is scaled as well.

90nm on a 300mm wafer produces 325 processors.

65nm and 90nm...

January = 10,833 wspm
50% 90nm = 5,416 wspm = 1,760,200
50% 65nm = 5,416 wspm = 2,664,672

February = 11,666 wspm
40% 90nm = 4,667 wspm = 1,516,775
60% 65nm = 6,999 wspm = 3,443,508

March = 12,499 wspm
30% 90nm = 3,750 wspm = 1,218,750
70% 65nm = 8,749 wspm = 4,304,508

April = 13,332 wspm
20% 90nm = 2,667 wspm = 866,775
80% 65nm = 10,665 wspm = 5,247,180

May = 14,165 wspm
10% 90nm = 1,417 wspm = 460,525
90% 65nm = 12,748 wspm = 6,272,016

All 65nm...

June = 14,998 wspm = 7,379,016
July = 15,831 wspm = 7,788,852
August = 16,664 wspm = 8,198,688
September = 17,497 wspm = 8,608,524
October = 18,330 wspm = 9,018,360
November = 19,163 wspm = 9,428,196
December = 19,996 wspm = 9,838,032

This gives you 5,823,025 90nm (January - May) + 21,931,884 65nm (January - May) + 60,259,668 65nm (June - December).

Thats 82,191,552 65nm and 5,823,025 90nm for the year from FAB 36.

FAB 38 65nm 300mm wafer

FAB 38 is supposed to ramp fast, from 0 - 20,000 wspm in 6 months.

July = 3,333 wspm = 1,639,836
August = 6,666 wspm = 3,279,672
September = 9,999 wspm = 4,919,508
October = 13,332 wspm = 6,559,344
November = 16,665 wspm = 8,199,180
December = 20,000 wspm = 9,840,000

That gives you 34,437,540 65nm (July - December).

So all in all we end up with 116,629,092 dual core 65nm processors and 37,675,525 dual core 90nm processors for 2007.

Or 154,304,617 total processors, now factor in Sharikous 90% yield and we get 138,874,155 processors.

The estimate for total micrprocessors for 2007 is about 250 million (2008 is about 275 million), using these numbers at 90% yield would give AMD enough capacity to supply 55% of the market.

This to me makes little sense considering AMD themselves have stated a capcaity goal of about 30% leaving 2007, and 40% leaving 2008.

Obviously there is a substantial problem.

-----------------------------------------

Before I finished this, I had looked on the blog and noticed this post...

"You need some area to actually cut the die!"

Since I had gotten lost in the numbers I had not thought about this.

Taking this into account, and using the wafer program it changes the total die per wafer substantialy.

Previously die width and height were at 11.5, spacer and margin were at 0.

Changing this to 11.25 width and height, and adding in a spacer and margin of 3mm, we end up with 298 processors.

298 * 100 / 492 = 60.56, or about 39% fewer processors per wafer.

Just a quick calc and we end up with (116,629,092 * 0.61) 71,143,746 65nm processors, and just to have an idea well do the same to the 90nm (37,675,525 * 0.61) 22,982,070 90nm processors.

Now when we total the number 94,125,816, and apply an 80% yield we are now right in between where AMD wanted to be in 2007 and 2008, 35% of projected capacity.

Now the numbers seem much more realistic.

PS: If you see an error just let me know, thanks.

9:23 PM, December 19, 2006  
Blogger Sharikou, Ph. D said...

Changing this to 11.25 width and height, and adding in a spacer and margin of 3mm

3mm die spacer? Take a ruler and measure this
picture of a 65nm wafer

10:01 PM, December 19, 2006  
Anonymous Anonymous said...

Why is there going to be a major clock bump on 65nm process next year?

10:09 PM, December 19, 2006  
Anonymous enumae said...

Sorry about that, I am tired as hell, whats that margin and spacer supposed to be, just let me know and I'll re do the numbers later-tomorrow.

Thanks

10:30 PM, December 19, 2006  
Blogger Sharikou, Ph. D said...

whats that margin and spacer supposed to be

I think the die spacer should be smaller than 1mm. Cutting silicon is just like cutting glass, you don't knock off a 3mm wide strip, you cut it by slicing a line. The die cutting machines have precision of a few micron.

On a CPU die, there should be margin areas with no transistors, but that area is already counted as in total die area.

11:00 PM, December 19, 2006  
Anonymous Anonymous said...

"The die cutting machines have precision of a few micron."

They may have the PRECISION of a few micron but the width of the cutting blade and Si loss is just a bit wider than 1 micron! think about what you are saying for a second here - is the width of the blade is a few um? On top of that you also have to leave a little margin of error for lining up the cut too (that would be where the precision part comes in)...

Wow you really do have no clue, I though you were just in spin mode again...

As for the 3mm - that is the edge exclusion dumbass... not all process steps go all the way out to the edge of the wafer thus you can't make working die all the way to the very edge...

Something else to think about you idiot - the wafer edge is beveled! (for mechanical reasons) I think the 300mm spec is ~0.5mm; that alone prevents you from making die all the way out to the edge of the wafer. (In case you don't believ my 3mm #)

Let me know when you've had enough...

"On a CPU die, there should be margin areas with no transistors, but that area is already counted as in total die area."

So at this point you're just spitballing here and just guessing... "should?" (meaning "in your opinion" or is this an actual fact that you can prove)

You also might want to take note that the die is not square and the exact x-y dimensions may also change die/wafer count (not sure in which direction) - this SHOULD have minimal impact compared to the more egregious errors in your calculations.

Also Si is a crystal, it is not like glass (amorphous) - cutting a crystal and cutting amorphous glass are 2 different things - but please just keep throwing things out there (you might get lucky and get something right eventually)

enumae: use 3mm (this is BEST case for AMD) for the edge exclusion and ~0.2mm for the die spacer. Just don't use Sharikou as a source for data like this...

Sharikou - please provide link supporting 90% yield data point.

12:23 AM, December 20, 2006  
Anonymous Anonymous said...

Yup 492 die/wafer - figured it out.

Sharikou used the wafer application at geek.com

He used the x,y values he indicated and the assumed 0mm edge exclusion and 0 die spacing...it took me while because I didn't think anyone was stupid enough to assume a 0mm edge exclusion.

Apparently Sharikou has learned how to print 35nm poly gates at the edge of the wafer which is beveled - yup depth of focus shouldn't be too much of an issue there; it's not like litho is that unforgiving at these feature sizes.. Oh, and some of those tools that use a clamp ring to hold a wafer - Sharikou apparently has invented a way to do the processing under these clamp rings... this and the lossless dicing process; I'm surprise he is not rich licensing all of this "IP"

Best case 450 die/wafer... with 100% yield and very aggressive scribeline widths...

of course Shari-kook's 200mm #'s are similarly off...

Now factor in overall yield %, scrap (small but not 0); capacity loss due to K8l being bigger die (isn't opteron a bigger die now than x2 also?), need for development lots (again small impact but not 0) and losses at sort/packaging and you will just start to scratch the surface of how his #'s are off

Yield assumption is probably the biggest error, die/wafer is the dumbest error (~10% error) and thirdly factoring in F30 conversion and even F36 (90nm to 65nm) conversion - not sure how much this is because with all of the other errors it's not worth the time figuring out...

1:10 AM, December 20, 2006  
Anonymous Anonymous said...

I've had enough. I'm finally going to say something. I can't stand to watch people mangle this word any more.

The plural or die is.... ready?

Die.

Not dies, not dice.

Die.

Ok, I've said it.

Carry on.

1:41 AM, December 20, 2006  
Anonymous Anonymous said...

AND

Die spacing is .5mm AT MOST.

I can't belive these lame assumptions. There have to be at least a few experienced people reading this blog. Please edit and correct as needed!

Sharikou, I like reading your blog, but you most ceartianly have never been in a clean room.

1:48 AM, December 20, 2006  
Anonymous roborat64 said...

Assuming your total Fab output is accurate for the first time:
41 million is the theoretical capacity - Fab true output (best case estimate) 95% (typical 90-95%) = 38950000
Subtract best case R&D, new product introduction, sample lots at 5% (usually 5-10%) = 37002500
Subtract Fab mechanical yield loss (defectivity, process missteps) best case 10% (usually 10-20%) = 33302250
Subtract Assembly mechanical yield loss (die to package) best case 10% (usually 10-15%) = 29972025
Subtract Electrical yield loss (bad die, low bin, infant mortality) best case 15% (usually 15 – 40% depending of maturity) = 25476221

25.4 million die per quarter is about 62% yield.

And this is just best case, not even Intel can achieve this consistently. AMD is lucky it can even get 50% wafer-to-unit yield on a process and equipment-set they did not develop themselves.
At 50% yield your 41 million is only down to 20.5 million. And this isn’t even taking into account their Fab transition.

sorry to burst your bubble.

3:07 AM, December 20, 2006  
Blogger 180 Sharikou said...

Doctor - instead of yanking numbers out of thin air, why don't you look at Bob Rivet's analyst day presentation. Page 19 - MPU capacity in 2007 a little under 100 million. In 2008 ~110 million.

Enumae - your calculation seems more accurate. Though redundant when the numbers are publicly available from AMD themselves.

http://sharikou180.blogspot.com

7:46 AM, December 20, 2006  
Blogger Dr. Yield, PhD, MBA said...

Our humble host writes:
On a CPU die, there should be margin areas with no transistors, but that area is already counted as in total die area.

Actually, the "street" or "scribe" is not included in the die, but a standard scribe, is roughly 150um (.15mm). This makes a difference, but not a huge one. Standard edge exclusion (margin in the program) is 3mm, but it is important to note that yield on the edge die after this tends to be extremely low- a 9-10mm "margin" would give you a better estimate of yielding die.

BTW, you are actually penalizing AMD by assuming a square die. If you look at die plots of the X2, you will see an aspect ratio of 1.2:1, which for a 126mm^2 part means ~5% more dpw.

To the above dpw numbers, you need to apply the process yields. Here, there are typically 2 numbers- wafer yield and die yield. Wafer yield is typically very high for everyone- in the 98-99+% range (hey, scratches happen), so it is relatively safe to ignore this in your capacity calc.

Unfortunately for everyone except for yield/metrology equipment suppliers, 65nm die yields are low across the board. Current estimates are actually in the 50% range- nowhere near 90%. For everyone's edification, I post 2 references:

AMD/Chartered-specific:
"The reports authors said that yields were at 50 percent at Chartered's Fab7 but sometimes even better than those achieved within AMD's own fab! "

KLA-Tencor Q12007 Conference Call
"Yield at 65-nanometer sincerely still in the steep learning part of the curve with most customers still well below 50% yield."

Based on the above, I think 90% is optimistic, even for end of 2007. Mature die yields on the smaller die 90nm products are probably in the 80-90% range, and the X2 at 183mm^2 is likely closer to 70% due to its size.

So what does this mean?
Assuming the die sizes above, your wspm numbers are correct (not using Enumae's), and 440 potential good dpw at 65nm, 116 pot. good dpw at 90nm, and 50% 65nm yield and 70% 90nm yield...

you get 11.9M 65nm die and 7.3M 90nm die for 19.2M total. 60% 65nm yield drives this up to 21.6M total die.

what happens if add some K8Ls to your mix?

Assume 10% of 65nm wafer starts go to K8L square die size of 16.8x16.8mm (based on die plots and estimates published on the web)for 188 pot. good dpw and a large die yield of 40%. You get ~400k K8Ls for your trouble, and a new quarterly total of 18.4M die (net give up 1.2M X2s to make .4M K8Ls). Even if you bump X2 to 60% and K8L to 50%, you give up 1.5M X2s to make .5M K8Ls. This is why integrated quad core is so risky for AMD from a cost perspective... but that should be another thread. If not, we can always discuss later.

Thoughts?

9:06 AM, December 20, 2006  
Blogger Sharikou, Ph. D said...

Even if you bump X2 to 60% and K8L to 50%, you give up 1.5M X2s to make .5M K8Ls.

Thanks for your analysis. AMD won't be producing AM2 quads until 3Q07, when FAB38 is ramping. Before that, you have Quad FX--two K8Ls, eight cores, enough to frag Conroe double die 3x.

9:33 AM, December 20, 2006  
Anonymous enumae said...

Dr. Yield, PhD, MBA said...

"Assuming the die sizes above, your wspm numbers are correct (not using Enumae's),..."

I am just curious what is wrong with my wspm?

Thanks.

10:34 AM, December 20, 2006  
Anonymous enumae said...

Sharikou 180 said...

"Enumae - your calculation seems more accurate. Though redundant when the numbers are publicly available from AMD themselves."

Where were you last night at 2:00am...lol

I forgot about that.

11:04 AM, December 20, 2006  
Blogger Sharikou, Ph. D said...

Doctor - instead of yanking numbers out of thin air, why don't you look at Bob Rivet's analyst day presentation. Page 19 - MPU capacity in 2007 a little under 100 million. In 2008 ~110 million.


AMD likes to hide the ball. In 2005, it projected 50million units for 2006. But, as you can see from the diagram, it's 65million.

11:13 AM, December 20, 2006  
Anonymous Anonymous said...

Sharikou, Ph. D said...
"Even if you bump X2 to 60% and K8L to 50%, you give up 1.5M X2s to make .5M K8Ls.

Thanks for your analysis. AMD won't be producing AM2 quads until 3Q07, when FAB38 is ramping. Before that, you have Quad FX--two K8Ls, eight cores, enough to frag Conroe double die 3x. "

And exactly what makes you think that Intel won't have an answer to this by then?

I guess I should be asking "What makes you think?" It certainly can't be your brain, pretender, because as far as I can tell, you have none.

1:15 PM, December 20, 2006  
Anonymous Anonymous said...

"Thanks for your analysis. AMD won't be producing AM2 quads until 3Q07, when FAB38 is ramping."

You have repeatedly said Q2! In one previous blog you even said you wouldn't be surprised if they pulled it into the end of Q1'07!

Now when it doesn't fit your argument you change this to Q3... the scary thing is you are finally now right - K8l will be such negligible volume this year, it just won't matter... I guess instead of changing it from K-9 to K8l they should just call it Kl8...

At least now you're no longer spewing misinformation on die/wafer with 0mm EE!

Enumae's WSPM is probably more realistic than the doctor's, although the F38 65nm ramp is probably too fast and/or the F30 ramp down to meet that ramp is too slow.

Ramping a factory from 0-20K in 6 months is unlikely (just look at F36 and that was a green-field site!) You simply cannot install this many tools in that time period - the only way this could happen is if tools were brought in early (which would imply 90nm would need to be ramped down more aggressively in F30 to make space.

People also need to remember that it is not just equipment tooling, 300mm uses an entirely different HW automation system (OHV) which affects tool layout, etc so it's not like you can just exchange a 200mm tool for 300mm tool.

Enumae - as an example at the same time (Dec'07) you have F38 at full 65nm build out you still have it producing 2.5K 90nm wafers...You need to offset the ramp up/ramp down by ~1 quarter. (When 65nm is at full build out that would mean 90nm was completed a quarter ago to allow for tool move-in, toool process qualifications, etc...)

1:38 PM, December 20, 2006  
Anonymous enumae said...

Anonymous said...

"Enumae - as an example at the same time (Dec'07) you have F38 at full 65nm build out you still have it producing 2.5K 90nm wafers..."

Yeah, the numbers arn't perfect and I will probably not redo them though since Sharikou180 pointed out the Bob Rivet's analyst day presentation, but its good to see you guys at least looked at them.

Thanks

1:53 PM, December 20, 2006  
Anonymous Anonymous said...

"AMD likes to hide the ball. In 2005, it projected 50million units for 2006. But, as you can see from the diagram, it's 65million."

I think the term is "sandbag". Given AMD's history on execution on technology/manufacturings ramps I think they are understating it in case they screw it up again. This was when they exceed the # they can say "look at how good we ware executing we are above preiovus projections!"

It's the same thing with "mid-2007" K8l release - I mean come on this is only ~4 months away and they can't provide better guidance on this? They put this window in so when it finally paper launches in Q3'07, they can say - look we delivered again!

They also recently announced a "release" date for next gen which I think was mid-2008 (or maybe mid-2009, I forget) - so they have the same level of precision 1-2 years out as they do in 4 months? Since when did a release date become "middle of [insert year here]" and not an actual month (or even quarter). These are not release dates these are "projections"...

I still don't even think the "65"nm product they are shipping is really 65nm - the die area scaling is terrible, and transistor performance is not any better than 90nm. I'm still waiting for someone to crack one of these open and look at the M1 pitch.

While CTI sounds good - it is a yield excursion waiting to happen some of the future changes (especially the stress changes) are very pattern and product dependent - they will need to keep tuning this everytime they do a CTI rev/change (meaning new mask sets, product quals, etc...)

Anyone with a process background have thoughts on this?

1:54 PM, December 20, 2006  
Anonymous Anonymous said...

Hilarious:

"90%yield" links to a powerpoint presentation by AMD which says "mature yield, low defect density"
(Did I miss the 90% part on the slide? Actually I thought you previously said AMD's mature yields are near 100% - you know, APM3.0! - so why not just use 100%?)

"PS: Some retards are wailing about this estimate. My suggestion, do your own math."

Translation: Some folks have pointed out errors in my calculation which are so bad even I can't backpedal from them so I'll just call them retards rather than tucking my tail between my legs and admitting I was wrong or running away to a new topic...

Well, we'll soon see who's right with your estimate of 37mil units for AMD and 20mil for Intel, that means AMD should have ~65% market share by the middle of next year correct? I see another prediction coming...

And I think you've also said previously once AMD gets above 50% market share Intel's BK is accelerated - this means your Q2'08 prediction needs to be pulled in now, no?

I hope you are at least pulling in some good google ad money....

2:50 PM, December 20, 2006  
Blogger Dr. Yield, PhD, MBA said...

Enumae shaped the electrons to say:
I am just curious what is wrong with my wspm?

Didn't pore over them, they looked reasonable from a first read. I just took Sharikou's numbers as an absolute best case scenario so that people would focus on the analysis instead of quibbling over the wspm issue.

Even with those numbers and no quad cores or test wafers in the mix (which I also didn't count as a consumer of capacity), the total was only 21.6M die, not 37M. HUGE difference, without even getting into the debate re: total wspm/fab.

You can revise the numbers accordingly, since I just applied yield and dpw to Sharikou's wafer starts.

3:54 PM, December 20, 2006  
Blogger Dr. Yield, PhD, MBA said...

I'm a little surprised no one is discussing the strategic implications of why Intel is driving quadcore so hard in the server space. By pushing 4 cores/socket into the space (no price premium to go from Woodcrest to Clovertown!), Intel is accelerating market acceptance of 4 cores/socket as a standard. Yes, Edward and others will correctly note that certain applications will still win on Opteron, but the shift in the "market standard" will be a real force to contend with, given that Clovertown does provide compelling performance.

So why does this matter for AMD? Based on the calcs in my earlier post, for every 1 K8L made, you lose 3 K8s made on the 65nm process. Why 3X? Because larger die yield lower- simple statistics, go back and search some of my earlier posts in Aug/Sep. Also because you simply can't pack the wafer as efficiently, so a 2.25X larger die gets >2.25X less dpw. (note bene: this also implies the cost effectiveness of Intel's 2 die MCM approach, even if it isn't elegant)

This ultimately means that if AMD is supply constrained for 2 core product, they need to sacrifice K8L production. Alternatively, they need to be making 3X revenue over standard X2 product per K8L in order to financially justify converting product- which means server only parts. Don't expect to see much by way of K8L until AMD is rolling in 65nm capacity. Ultimately, manufacturing muscle is critical in this business- and Intel is flexing that muscle a lot with the quad core drive...

Anyone disagree? If so, tell me where I'm wrong- but spare me the AMD Roolz Intel Suxz Roxz with old P3 tech argument.

4:09 PM, December 20, 2006  
Blogger Sharikou, Ph. D said...

Did I miss the 90% part on the slide? Actually I thought you previously said AMD's mature yields are near 100% - you know, APM3.0! - so why not just use 100%?

I heard AMD's 90nm mature yield was indeed near 100%. Mature means it can't get any better.

For Bob Rivet for use the words "mature yield, extremely low defect density", 90% yield must be assumed. A 70% yield is not mature yield, and 30% bad dies are not extremely low.

APM 3.0 makes all the wonders.

4:21 PM, December 20, 2006  
Blogger Sharikou, Ph. D said...

I'm a little surprised no one is discussing the strategic implications of why Intel is driving quadcore so hard in the server space.

Intel's only chance to stay in the server market is to push quad core. Right now, AMD's top line if 8P 16 core. Intel's top line is 2P 8 core -- two clovertowns are much faster than 4 Tulsa Xeons. Soon, AMD's top line will be 8P 32 core, Intel is out of the game at the high end, that is for sure.

4:30 PM, December 20, 2006  
Anonymous Anonymous said...

"For Bob Rivet for use the words "mature yield, extremely low defect density", 90% yield must be assumed. A 70% yield is not mature yield, and 30% bad dies are not extremely low."

Wow you really are ignorant - 90% must be assumed? Just because something is mature doesn't mean it should be confused with perfect.

What is the batting average of a baseplayer when he matures as a hitter, 1.000? What is the transistor speed of a "mature" 130nm process? infinite?

Mature can (and in this case, should) be interperted to mean it is unlikely to get any better - that doesn't necessarily mean 90%...

You can liken this to your knowledge about Si processing and manufacturing, as you refuse to take any inputs, assimilate new data, your knowledge has "matured" in this area. Unfortunately it has mature to an 8th grade level. However it is mature because I don't expect it to get any better!

"I heard AMD's 90nm mature yield was indeed near 100%."

I heard it was 10%, no wait 50%, no wait what # should I make up next... With all of the errors in this post it is pretty obvious you are just making stuff up so unless you plan on providing some data/links I wouldn't expect anyone to believe you...

BTW - still think AMD makes die all the way out to 0mm edge exclusion; you've been rather silent on that one other than calling people retards... I would appreciate your insight in this area and enlightening us retards as it would truly represent a remarkable breakthrough in Si processing.

Also any thoughts on AMD's remarkable 33% die area scaling between 90nm and 65nm products? (I believe you were expecting 50%, no?)

4:56 PM, December 20, 2006  
Anonymous Anonymous said...

Dr yield - you are dead on and this is the same boat as when Intel pushed dual core adoption all the way down to low end desktop...

Everyone can bad mouth the MCM approach all you want but it is by far better economically (as dr yield man pointed out).

The other financial component missing from dr yield's analysis is bin splits at high end frequency - for top bin AMD now needs all 4 cores above that fmax, while intel can mix and match 2 high speed dual cores. Same situation for power consumption! This means MCM approach is much more likely to bin out better on high speed parts (all other things being equal)

Now while some fools will say AMD's bin splits are constant and perfect across the wafer due to APM3.0 and their world class manufacturing capabilities, this is not the case in the real world of semiconductors...

5:12 PM, December 20, 2006  
Blogger 180 Sharikou said...

Dr. Yield - Intel's intent is to try and squeeze AMD's capacity yet again. Just like they did somewhat with dual core this year thereby forcing AMD to trim some SKUs and short supply the channel.

I refer to it here:
http://sharikou180.blogspot.com/2006/12/quad-fx-or-is-it-quad-just-for-effect.html

I believe they will be even more aggressive on quad core (server/desktop/mobile) than they were on Pentium D because now they have a decent architecture to sell. And, I also think they have too much capacity.

Doctor - do you have a link to substantiate this:
In 2005, it projected 50 million units for 2006

7:43 PM, December 20, 2006  
Blogger Sharikou, Ph. D said...

Dr. Yield - Intel's intent is to try and squeeze AMD's capacity yet again.

This is joke. Intel will exit 2006 with 25% Core 2 Duo. It will be lucky to get to 50% core 2 duo by 3Q07.

Intel is making last ditch effort to stay in server biz ahead of K8L onslaught.

7:49 PM, December 20, 2006  
Blogger Sharikou, Ph. D said...

Mature can (and in this case, should) be interperted to mean it is unlikely to get any better - that doesn't necessarily mean 90%...


Yes. We interpret the word "mature" the same way.. Now, the question is what the theoretical maximum yield is.

7:59 PM, December 20, 2006  
Blogger Sharikou, Ph. D said...

"I heard AMD's 90nm mature yield was indeed near 100%."

I heard it was 10%, no wait 50%,


AMD used to take 20% of the market with one 200mm FAB. We had to conclude that AMD's yield was near 100%, and Intel's yield is a fraction of that. See my anicent posts on that analysis.

8:01 PM, December 20, 2006  
Anonymous enumae said...

Sharikou said...

"Intel will exit 2006 with 25% Core 2 Duo."

Thats fine, maybe less than 25%, look here.

But, just for an example and some perspective...

Total market capacity is 100 units.

Intel = 75
AMD = 25

If Mobile is 33%, Desktop is 33% and Server is 33%, here are some hypotheticals.

AMD desktop... 25 / 3 = 8.33
Intel Desktop... 75 / 3 = 25

Theoretically if Intels gets Core 2 Duo to 33% on the desktop and Intel (Sharikou logic) frags AMD. And leaves Intel with another 50% of the market to sell there remaining products.

AMD Mobile... 25/3 = 8.33
Intel Mobile... 75/3 = 25

Again, theoretically if Intels gets Core 2 Duo to 33% in the Mobile segment Intel (Sharikou logic) frags AMD. And again leaves Intel with another 50% of the market to sell there remaining products.


AMD Server... 25/3 = 8.33
Intel Server... 75/3 = 25

Servers are not my thing and there seem to be alot more variables here, so well let amd have that one, which gives them the ability to frag 33% of the Server market. And yet again leaves Intel with another 50% of the market to sell there remaining products.

Thats 50% of each segment.

PS: These are just theoretical.

9:43 PM, December 20, 2006  
Anonymous Anonymous said...

"AMD used to take 20% of the market with one 200mm FAB. We had to conclude that AMD's yield was near 100%, and Intel's yield is a fraction of that. See my anicent posts on that analysis."

First off, "we" is a nice way of saying I'm the only one who believes the crap I'm spewing, but we makes it sound like it is a generally accepted fact...

Your analysis in the past is off, just like it clearly is today (which is a fact that you've been trying to divert people from, because even you know it's now wrong). Are you sticking by your current analysis given some of the comments on this blog?

Answer this SIMPLE QUESTION - if AMD is truly capacity constrained (which I personally believe to be true), how are they not ALREADY at >40% market share given you capacity analysis?

(Heck your own analysis shows AMD able to produce ~60-65% of the market by mid-year 2007...) Given that F36 is already >50% 65nm converted how does AMD not already have 50% market share if your analysis is so good?

Here's some possible conclusions:
A) AMD is not really capacity constrained (which I think all would agree is not the case)
B) AMD already has >50% market share and the numbers are not being reported (or maybe Intel is paying people off not to release them?)
C) Perhaps, just perhaps, your capacity analysis is off (due to yield assumption, die per wafer, wafers starts...)

I'm not a betting man but I would put my money on"C". If you think I'm wrong please provide me a plausible alternative to why AMD is not at 40-50% market share today!

9:50 PM, December 20, 2006  
Blogger Dr. Yield, PhD, MBA said...

We had to conclude that AMD's yield was near 100%, and Intel's yield is a fraction of that. See my anicent posts on that analysis.

You may feel free to conclude whatever you like, but you would be quite wrong. No I can't post links, nor will I reveal sources. Let's just say that back in the days of 150mm (6") wafers, perfect wafers (100% die yield, including edge die) were a once or twice a fab lifetime events (processlife cradle to grave of say 5-6 years). % die yield is always a function of die size. Big die ALWAYS, by definition, yield worse than small die.

As to the gentleman who posted above that I neglected to mention the bin split advantages of smaller die, you are dead on. In addition to dealing with fmax on all dies on a chip, you also have increasing CD variation as die size goes up. This is because the die grows larger than the sweet spot of the scanner lens, and you tend to see larger aberrations as you move radially from the center of the lens. For those of you who don't know, CD variation directly correlates to transistor switching speed (larger=slower) and leakage (smaller=leakier).

Good thread everyone- all of us retards and fake doctors (I believe it was Edward who spewed that one at me) are discussing this rather well. Who knows, maybe we'll hijack the blog to a level of enlightenment seen over at Scientia's blog... :)

9:50 PM, December 20, 2006  
Blogger Sharikou, Ph. D said...

if AMD is truly capacity constrained (which I personally believe to be true), how are they not ALREADY at >40% market share given you capacity analysis?


I projected a 40% run rate for AMD market share, that number is looking very solid right now.

10:26 PM, December 20, 2006  
Blogger Sharikou, Ph. D said...

As to the gentleman who posted above that I neglected to mention the bin split advantages of smaller die, you are dead on.

The advantage of APM is it produces uniform dies due to APM's ability to adjust every single transistor on the fly... AMD processors are uniform, they are just clocked differently. For instance, you don't see dual cores at lower than 2GHZ, while for single cores they go as low as 1.6GHZ. For the 65nm node, the lowest clock is 2.1GHZ. The whole thing about APM is precision. That's an advantage. Chartered FAB7 was having big problems with yields. APM saved the day.

APM is like fly-by-wire, if you know what I mean.

10:31 PM, December 20, 2006  
Blogger Sharikou, Ph. D said...

Big die ALWAYS, by definition, yield worse than small die.


When the yield is approaching 100%, die size doesn't matter any more. Bob Rivet claimed extremely low defect density--the beauty of APM.

10:34 PM, December 20, 2006  
Anonymous Anonymous said...

"AMD used to take 20% of the market with one 200mm FAB" (this in your mind proves near perfect yield?)

Let's ASSUME YOUR 200mm 90nm F30 CALCULATION IS PERFECT in this blog (of course it is not but just to show how absurd you are...).

By your calculations if AMD was producing 100% DUAL CORE they would produce 12.3mil potential die/qtr

With PERFECT yield we will carry this # over to actual die out.

However we now have to correct for the fact that AMD was not selling 100% dual core back then so the total die out should actually be much higher than this... Back in the days of only F30, dual core must have been at most 30%... so let's ratchet theoretical maximum to 15mil (conservatively due to smaller die area of single core)...

So if 15mil was 20% market share, then the entire x86 market would be 75mil CPU's/qtr

See the problem yet.... TODAY's market is not even 75mil/qtr yet alone a couple of years ago! (according to you in this blog it is 37mil+20mil = 57mil/qtr)

So if AMD had 20% market share how can this be the case?

A) They sat on a bunch of CPU's (which isn't the case because we would see inventory on their balance sheet as well as inv write-offs)
B) They were lying about F30's WPSM capacity (I think this unlikely)
C) They were not running F30 at full bore i.e. it was capable of 30K WPSM but for whatever reason they were not operating at 100% capcity (I find this unlikely as they've been caapacity constrained for sometime and would seemingly want to produce as many die as possible)
D) Maybe, just maybe out of all those theoretical die, some of them may have not yielded, after all they weren't on APM3.0 back then! ;)
E) You are completely off with your F30 capacity calculation in this blog.

The answer is both D & E - your 200mm die/wafer calc is off because you fail to recognize the concept of edge exclusion and die spacing and obviously yield is not 100% yield (see calculations above).

Your numbers are just not self consistent... was your F30 calculation wrong way back then or is it wrong in this blog?

The real funny thing is both calculations are wrong (as opposed to just one of them being wrong) because both your yield ASSUMPTION and 200mm die/wafer ASSUMPTION are wrong. The only thing funnier than this is your inability to acknowledge this despite being presented with overwhelming evidence of your mistakes...

10:37 PM, December 20, 2006  
Anonymous Anonymous said...

"I projected a 40% run rate for AMD market share, that number is looking very solid right now."

You dodged the question - WHY IS AMDY NOT AT 40% MARKET SHARE RIGHT NOW OR FOR THAT MATTER LAST QUARTER?

According to your calculations AMD is ALREADY above the 40% capacity level (and will be near 65% by end Q2'07 when F36 finishes 65nm conversion)

Finally please define (mathematically) market share runrate. You have refused to answer this multiple times now. What was AMD's Q3 market share (runrate)?

I'm really hoping you're not going to try to say 40% growth rate in market share... (yet somehow this is where I see you heading to try to back out of the prediction). Although thankfully 40% growth rate on 25% market share is still 10% absolute growth, so there's little chance of that happening too... I just hope Via goes from 1% back to 2% so we could say Via's market share runrate is 100%!

10:56 PM, December 20, 2006  
Anonymous Anonymous said...

"You dodged the question - WHY IS AMDY NOT AT 40% MARKET SHARE RIGHT NOW OR FOR THAT MATTER LAST QUARTER?

According to your calculations AMD is ALREADY above the 40% capacity level (and will be near 65% by end Q2'07 when F36 finishes 65nm conversion)

Finally please define (mathematically) market share runrate. You have refused to answer this multiple times now. What was AMD's Q3 market share (runrate)?"

He will always dodge questions he doesn't understand. He will always refuse to answer any question that even remotley puts AMD in a negative light.

This blog has nothing to do with anything but trying to make Intel look bad because Intel canned this poser.

Moronic behaviour led to him being unemployed so he thinks he can wish Intel into bankruptcy by his uninformed, unintelligent posturing, that he props up by falsely claiming to be a ph.d and a journalist. In point of fact he is neither.

I'm sure someone will ask why I come here and my answer is that I have a "Humor" section under my favorites in my browesr, and thats where the link to this blog falls.

BTW - once you claim to be a journalist, most of the protections that are afforded a person on a blog in terms of avoiding legal action against you are void. Just an FYI.

9:07 AM, December 21, 2006  
Blogger Sharikou, Ph. D said...

By your calculations if AMD was producing 100% DUAL CORE they would produce 12.3mil potential die/qtr


FAB30 only recently reached 30000wspm. It was like 25000wspm before or even lower. Of course the average die size was also smaller becase most CPUs were single core--but there were also larger dual cores with 2MB cache. Just do the math, you will find the yield is close to perfect.

I had to admit that AMD's ramp on FAB36 was quite slow. If you look at AMD's graphs, FAB did not produce much until the middle of 3Q06. Now with DELL signed up, the situation changed completely.

11:17 AM, December 21, 2006  
Anonymous Anonymous said...

OK, here's the math (WITH ALL OF YOUR BS ASSUMPTIONS WHICH HAVE BEEN EXPOSED)

Let's keep F30 at 25K WSPW as you say...

25K/month * 3mo/qtr * 137die/wfr *100% yield = 10.3mil DUAL CORE die/qtr

Dual core die = 183mm2, single core
~147mm2, this is ~25% smaller, assume ~30% dual core mix and this means die # should be adjusted by an aggregate of 25%*70% =17.5% (this is crude approximation).

So adjusting the 10.3 mil for the 17.5% smaller die will yield ~11.5Mil (I'm rounding liberally)

At 20% market share 11.5Mil translates into total market size of 57.5mil/qtr which is the size of TODAY'S market!

So Sharikou was right! Well actually no, see the CPU market tends to grow each year. Yes, I'm quite certain I've read that somewhere...

SO even using ALL OF SHARIKOU'S #, the #'s are still >20% off (yield not 100% anyone, Beuhler, Beuhler, anyone?!?)

Now what I would like to see is Sharikou DO THE ACTUAL MATH....pot...kettle...black...

Be careful with your assumptions, because when ou ASSUME you make an ASS out of U and...well just you!

1:09 PM, December 21, 2006  
Anonymous Anonymous said...

Slow ramp, fast ramp - AMD now has the wafer starts in F36 and is 50% converted to 65nm, no?

So why is AMD not at 40-50% market share today? Forget runrate, etc... If they currently can produce at least 40-50% of the world's supply TODAY as you claim; Why does their CURRENT market share not reflect this? They are not building significant inventory according to their financials and as you have stated so eloquently "they sell every chip they make before the wafer is even started". COuple this with the fact that they still produce a signifcant # of single die then their market share according to your calculations should be even higher!

So 2 simple questions

1) given all this capacity as you have so eloquently calculated... WHY IS AMD NOT ALREADY AT >40% MARKET SHARE!?!?

2) Given your calculation in this blog of AMD able to produce 37mil CPU/qtr when F36 is fully converted to 65nm end Q2'07), are you now predicting AMD will be at >60% market share by end Q2'07?

1:19 PM, December 21, 2006  
Blogger Sharikou, Ph. D said...

1) given all this capacity as you have so eloquently calculated... WHY IS AMD NOT ALREADY AT >40% MARKET SHARE!?!?

2) Given your calculation in this blog of AMD able to produce 37mil CPU/qtr when F36 is fully converted to 65nm end Q2'07), are you now predicting AMD will be at >60% market share by end Q2'07?


Good questions. So that you know, I always answer good questions.

1) How do you know AMD is NOT at 40% market share?

2) I would estimate a close to 50% market share by the time FAB36 is fully converted to 65nm. Let's give AMD folks some lowered expectations.

If I were Hector Ruiz, I would only make dual core and high clock single core CPUs, and sell them at around $100, flood the hell of the market.

3:16 PM, December 21, 2006  
Blogger 180 Sharikou said...

Doctor - how many times must I request you not to make stuff up:

Sharikou, Ph. D said...

Doctor - instead of yanking numbers out of thin air, why don't you look at Bob Rivet's analyst day presentation. Page 19 - MPU capacity in 2007 a little under 100 million. In 2008 ~110 million.


AMD likes to hide the ball. In 2005, it projected 50million units for 2006. But, as you can see from the diagram, it's 65million.


Now here's a link to Bob Rivet's November 2005 Analyst Day presentation:

http://www.amd.com/us-en/assets/content_type/DownloadableAssets/Bob_Rivet_AMD_Analyst_Day_11-15-05.pdf

Let's see...the numbers look exactly the same as they do a year later - 60+ million units. It distresses me to have to continuously point out your fabrications.

4:15 PM, December 21, 2006  
Anonymous Anonymous said...

"1) How do you know AMD is NOT at 40% market share?"

As of end of Q3 AMD had something around 23% market share... and had most of this magical capacity in place that you are talking about
- F30 @ 30K which equals ~20+% market according to you (12.3mil/57 mil)
- We'll conservatively say F36 was only at 10K WPSM @ 90nm, multiply this by 2.25 (approx for 300mm wafer area upside) and this is roughly 22K WSPM of 200mm equiv (or another 15% of the market).

So at end of Q3, AMD should have been in the 35% market share range (AGAIN USING YOUR BS MATH) - and they weren't... actually should have been even higher if you factor in single core mix..

The only way this works is if AMD had inventory the size of it's Q3 revenues (which it doesn't), your die/wafer is off (which it obviously is) and your yield estimate is off (which it also obviously is)

You we'll shortly see the Q4 #'s (about a month or so) and realize you really screwed up the capacity calculation.....

"I would estimate a close to 50% market share by the time FAB36 is fully converted to 65nm. Let's give AMD folks some lowered expectations."

So by your mathe AMD will be piling up over 10% of its sales in inventory... remember you estimate AMD will be able to produce 37mil out of the 57mil market when F36 is fully converted - this is MUCH more than 50% market share... are you expecting a yield excursion on 65nm ?

Only a fool will refuse to look at new data and revise a theory when the data utterly disproves the original hypothesis...one would think a PHD would understand this.

4:25 PM, December 21, 2006  
Blogger Sharikou, Ph. D said...

So at end of Q3, AMD should have been in the 35% market share range (AGAIN USING YOUR BS MATH) - and they weren't... actually should have been even higher if you factor in single core mix..


No. If you look at the die output graph, AMD's die output from FAB36 in Q2 was quite small, and it takes a while to make a CPU from a die. So AMD did not enjoy a big increase in CPU output in Q3.

4:35 PM, December 21, 2006  
Anonymous Anonymous said...

"Expect AMD to improve its 65nm transistor soon, and expect major clockspeed bump sometime next year."

READ: Current 65nm transistor performance (speed) sucks and is no better than 90nm despite claims that 65nm is 30% (or was it 40%, I forget) better performance claims by IBM/AMD.

APM3.0 BABY! Apparently able to tune every individual transistor on a wafer (yeah right) but not able to make a 65nm process any better than 90nm....

OR READ: The current "65"nm product is not really a mature 65nm process, it is an intermediate step beacuse we could not get the final 65nm transistor process development done with good enough yield...but really we are only just 1 year behind Intel, what matters is not actual process performance just that we ramped a crappy scaled 90nm transistor...Forget the fact that Intel did this out the door 1 year ago at the START of their 65nm ramp...

4:43 PM, December 21, 2006  
Anonymous Anonymous said...

"and it takes a while to make a CPU from a die. So AMD did not enjoy a big increase in CPU output in Q3."

Your argument is not rational - look at page 5:
http://www.amd.com/us-en/assets/content_type/DownloadableAssets/DarylOstranderAMDAnalystDay.pdf

If you look real close you may notice that 300mm output is nearly 50% of 300mm WAFER output in Q3'06!

Note:
- these are wafer outs (not starts), so you do not need to factor in processing time as these are finished wafers.
- this is in terms of wafers, with your world's perfect yield this would mean that in Q3 300m die out was actually HIGHER than 200mm die out! (when accounting for 2.25x Si area on 300mm wafer)
- Let's assume your 1 quarter packaging time kicks in and look back at Q2'06 outs... 300mm was 1/3 of 200mm wafer outs, multiply by 2.25 and 300mm die out should have been at ~70% of the 200mm level...

So one more time, WITH perfect yield and 300mm production being 70% of 200mm die production (assuming a ridiculous 1qtr time to package)... why was AMD not at well over 30% in Q3 (F30 = 20% in this scenario and F30 = 14%)

This ASSUMES perfect yield, 1 quarter to package a chip, all dual core, ability to make die to the very edge of the wafer and every other ridiculous assumption Sharikou has thrown at me...

For those who do care - while F30 was ONCE able to produce 20% of the market, it no longer can because the market (and AMD sales) has moved to greater mix of dual core (read - larger) chips. The fact that the market share of AMD is not 30-35% today indicates they are not getting the # die/wafer that Shari-kook believes.

This once again is because:
- Die are not made out to 0mmm EE like Sharikou thinks and there is small but finite spacing required fdor dicing process(in the real world 3mm is the target and as another reader pointed out the yield drops rapidly when you are within 10mm of the edge) This yield a ~10% die/wafer overstatement error (look up chipgeek.com wafer application if you want to play with some of the #'s)
- Overall yield is not near 100% (I know this is a remakable insight on my end!)
- There is larger aggregate die size (due to greater dual core mix)

FYI - it does not take a quarter to package a wafer... if so this would mean 2 quarters from starting Si to finished chip (~13 weeks for Si processing, and this "1 quarter" for packaging).

So for K8l to come out in June I sure hope AMD is starting the Si now! Hopefully the INQ will have a Christmas story on this.

And on that note - Merry Christmas/Happy Holidays everyone!

5:20 PM, December 21, 2006  
Blogger Dr. Yield, PhD, MBA said...

Our humble host blurted out:
The advantage of APM is it produces uniform dies due to APM's ability to adjust every single transistor on the fly... AMD processors are uniform, they are just clocked differently.

Ok, let me put this simply: the above statement is the most unadulterated pile of horseshit I have EVER heard.

I have been working in the field of lithography and design for over 10 years. I have attended countless conferences. No one- not AMD, not IBM, not any of the software or hardware vendors- claims to be able to control the patterning of each transistor separately. You sir, are clearly way out of your league AND have absolutely no idea what APM 3.0 can and can not do. It is a powerful tool, but it is not, I repeat NOT a panacea for the ills of patterning. I can cite countless peer-reviewed articles in the industry that attempt to minimize CD variation through physical manipulation of the layout, various and sundry optical resolution enhancement techniques, and even die-by-die or mask field-by-mask field dosage adjustment. But none of these allow one to tune individual transistors on every die of every wafer. None of them. Believe you me-if it could be done, it would be. But it ain't.

I would have responded to this ridiculous claim earlier, but I was actually on the road- maybe even inside a real life fab that makes real life wafers with edge exclusions, scribelines, and cool, whizbang factory automation. Or maybe not.

5:54 PM, December 22, 2006  
Blogger Scientia from AMDZone said...

Where did you get the 18K wspm? At the end of 2006 FAB 36 will be at 10K wspm.

FAB 36 will be at 15K wspm by mid 2007 and 20K wspm by end of 2007. Then capacity will top out at 25K wspm in mid 2008.

BTW, 90% is not mature yield. 70% can be considered mature yield.

I can also assure you that your 39 million a quarter estimate is not only high; it's really high.

A better estimate of total cpu production for all of 2006 is 65 million cpu's. The production during 2007 should be around 80 million and will reach 100 million in 2008.

Now, considering that these figures come from AMD itself, I wonder who we should believe?

2:25 AM, December 25, 2006  
Blogger Scientia from AMDZone said...

And, just to add. One of the anon posters is correct. By the time FAB 36 is at 15K in mid 2007 FAB 30 will already be down in capacity since the draw down begins mid Q2 07. Basically, FAB 30 draw down begins as soon as the new bump and test facility is ready.

2:31 AM, December 25, 2006  
Blogger Scientia from AMDZone said...

And, I'm also going to have to agree with Dr. Yield. APM is not capable of adjusting every single transistor, no lithographic process is. APM is a blanket technique, not a nano-surgery technique. Think of it more this way. If you analyze wafers in a batch and realize that the doping chemistry is a little off you may be able to adjust this in a later stage to bring the specs closer to what you want. However, you have no ability to fix one transistor.

2:39 AM, December 25, 2006  

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