K8L (Rev H) server/desktop for 2Q07
Charlie at INQ get tired of speculating and asked his contacts at AMD on the K8L question. The answer is AMD will launch Rev H quadcore in 2Q07. The first version will be using HT2.0, probably at 1.2GHZ to 1.4GHZ, up from 1GHZ. In 4Q07 to 1Q08, the HT links will be upgrade to HT3.0, with all those wonderful features.
On performance of the cores, we already know, 60% increase in integer speed, and 200% increase on floating point. Dirk Meyer told us AMD will have a faster core in 2007. He was true to his promise.
Power consumption will be 68 watts to 120 watts, which is not that surprising. Turion X2 is 31 watts.
We can safely say Intel is finished. Just as Conroe ramps up, AMD pushes Intel back by at least three years.
Back of envelope calculation for AMD's capacity in 3Q07:
FAB36: 25000wspm, 100 % 65nm, K8L dual core die area 110mm^2, plugs this data into the wafer.exe program with a geometry of 11x11. We got 540 K8L dual core candidates off one 300mm wafer. Quarterly K8L (DC) candidates will be 540* 25000 * 3 = 40.5 million. Annual die output will be 160 million.
FAB30: 100% dual core AM2 production, 182mm^2 die size, 30,000wspm ramped down to 15K wspm, 90nm. Using a geometry of 14x13.5, each 200mm wafer makes 144 dual core AM2 dies. Annual AM2 die output is this 144 * 12 * 15000 = 25.9 million.
Chartered FAB7, let's throw in 5000wspm, at 65nm, that's 32 million K8L dies.
Total: 160+25.9 +32 = 217.9 million dual core CPU dies (K8L and AM2). So far so good?
posted by Sharikou, Ph. D. @ 9/16/2006 02:00:00 PM
75 Comments:
"60% increase in integer speed, and 200% increase on floating point."
Proof please. And what do those numbers really mean? AMD beats Intel handily in Memory Bandith tests, that doesn't show up on gaming/encoding tests.
You also forgot to mention the fact that in the article you linked, 65nm will be December at the earliest:)
Same thermal envelope and drop-in pin compatible are examples of AMD doing the right things. At this moment, I see Intel kept getting punched one-oucha-two. How many more punches can Intel take?
Without CSI to compete against AMD's DCA, how many more punches can Intel take?
And how many blunders can a company make and still survive. So, FB RAM is the latest blunder right?
-Longan-
P.S. I really hope AMD has 60% market share and Intel 40%. I think most Oregon's 17,000 employees will be safe even at 40%. We are cheap here!
How do we know 60% integer and 200% floating point? Is that over current AMD or Conroe?
Is this also assuming that Intel sits on its hands until 2Q?
Finally, Sorry man but Conroe and Merom are ramped. I havnt seen any delays in availability from any vendor.
Its 2003 all over again. lol (K8 Wooped P4.) *Cough* Da'ja'voo all over again!
By the time that K8L ramps in desktop(Q407/Q108 earliest), Intel will bring Nehalem, Core 3:)
Promise Promise Promises
Someone pretender said "We can safely say Intel is finished. Just as Conroe ramps up, AMD pushes Intel back by at least three years."
Yeah what evidence is there. Where is the silicon, where are the bencharks in silicon. Promise Promises.
By then INTEL will have samples 45nm out by then.
Yawn...
Not a pretender, nor a fanboy!
Sharikou said...
"Just as Conroe ramps up, AMD pushes Intel back by at least three years."
Do you believe that Intel will make the same (Netburst) mistake again?
"Power consumption will be 68 watts to 120 watts, which is not that surprising."
Please check my numbers (everyone)... :)
I am a little surprised that you have made no mention to the 4MB's of cache (L2 and L3) on K8L (not including the 256KB of L1), and how that will effect its TDP, and since it hasn't been stated that this image is strictly Server and Workstation, I am going to assume it is Desktop as well.
The release of the X2 5200+ (2.6GHz) has a TDP of 89W, 24W of which is the addition of 1MB of cache.
90nm...89W - 48W (2MB cache) = Processor TDP no cache 41W.
[0.72 = 65*100/90]
65nm...(41W*0.72)30W Dual core = 60W Quad core no cache.
65nm Cache (24W*0.72)17.3W per MB * 4 = 69W for cache.
Quad core at 2.6GHz 60W + 69W = 129W
[0.46 = 1.2*100/2.6]
Quad core at 1.2GHz (60W*0.46) 27W + 69W = 96W
Looking at the numbers, it would seem there will be a few versions of K8L in order to reach the 68W your claiming.
Quad core at 1.2GHz with 3MB cache (1MB shared L3 and 512KB L2 per core) would be at 78W.
There is another factor in which I can not extend any knowledge and that is the manufacturing changes going to 65nm SGoI, and how those will relate to TDP. I am hoping you or someone else could let me know what kind of advantage SGoI will have and if it will then reach your numbers.
In conclusion, if SGoI can create a 10% drop in TDP the 2.6GHz would be at or near the 120W envelope you stated, but that doesn't leave much room for raising the clock speed above 2.6GHz.
Any comments would be appreciated.
Thanks in advance.
Hey Sharikou, if you've got the answer for me I'll save alot of time on research.
I want to try and find a BIO/profile for each of AMD's dream-team engineers.
I know you posted a list of all the architectures for which these engineers worked on, but I'd like to have the names too (if you know them) so that I can read up whatever I can find for each of these guys.
Thanks!
You can't possibly expect to believe that story with it's Barcelona, Shanghai, and Budapest. Whatever happened to Deerhound, Greyhound, Zamora, Wolfhound, and all the other "hound" cores we've been hearing about?
http://en.wikipedia.org/wiki/AMD_K8L
http://www.translate.ru/url/tran_url.asp?lang=ru&url=http%3A%2F%2Fwww.ixbt.com%2Feditorial%2Famd-guiseppe-amato-conf-part1.shtml&direction=re&template=General&cp1=NO&cp2=NO&autotranslate=on&psubmit2.x=14&psubmit2.y=12
http://upload.wikimedia.org/wikipedia/commons/thumb/1/15/Deerhound_QC.png/636px-Deerhound_QC.png
http://www.ixbt.com/editorial/amd-guiseppe-amato-conf/100.png
K8L and its arc's secrets... The next gen cpu for AM2/AM3 the 1st cpu to support 2 generations of sockets.
K8L has wider closer together threads to enhance its cycles per clock. Will process data much faster then K8 does. Plus the word is they will go upto 4ghz with K8L according to the Inquior microprocessor news page. The arc on paper can do it so I wouldn't be surprised. You got to understand this is a new arc. K8L and K8's are in a whole different ball leuge!
K8's are still impressive because they are 3 years old and still do this well. Zram is in K8L, the L1 L2 and L3 is 4x smaller in the die shots then K8 L2 but the same size in Kb such as 512kb L2. Sram would take up far too much space to add that much L3 L2 and L1 all on the same die when its smaller then K8 dies.
The manufacturing costs have been reduced because they are going 65nm on the cpu die and 45nm on the zram die. As why its so much smaller and denser. Zram is more proffitable and will improve performance L1 L2 and L3 by 10% as well as the chip. 256-bit Zram with 128-bit wide pipes.
They have 2x the FPU and x1/4th the ALU, with more out of order load buffers and a 4th decoader... this will atleast boost the FPU for SSE by 50% physically because of the extended FPU is 2x the size it was before. And the ALU will be increased from 25% to 50% by spec alone. Physically this makes opervation possible of what it will most likly beable to do.
K8L will be the new SSE monster on the block and will most likly have SSE4a on launch or later on. Atleast we'll get the Ghz wars like we wanted all over again.
the FPU 50% faster. K8L will be clocked much faster as well thanks to 65nm and the enhancments that allow it. Look at the load buffers and decoaders on die shots over the net. This move was made to allow higher clock speeds then previously not possible. K8L has deeper stages as well. Its sipose to use Double stress on SOI to allow greater speeds as well as a few other things, I think a new kind of gate in the manufacturing process. Those are really advanced FAB things they are doing... it takes 2 times longer to make these chips then intels because of the complexity of these added processes intel doesn't use.
Silicon Germanium (e-SiGe) with Dual Stress Liner (DSL) and Stress Memorization technology (SMT) on Silicon-On-Insulator (SOI) wafers, will be in K8L and allow these greater clockspeeds or cicles per clock K8's don't use all these processes, only K8L will. I'm not sure witch way AMD will go... the way of conroe in cycles per clock or the P4 as in uping the Ghz.
The new process technologies reduce interconnect delay through the use of lower dielectric constant (lower-K) insulators, which can improve overall product performance and lower power consumption. In addition, the new technologies have shown ability to be manufactured at the 65nm generation and scaleable for use in future generations. So expect some performance jump from 90nm to 65nm as well.
We still don't know how the real product will perform so until then we can only speculate or give oppinions but specs look promising. Soon we will see K8L in the wild so until then. Prob around dec we'll hear of (ES)!
Even the Rev G K8's got a face lift with simmilar decoaders and buffer enhancments as K8L so they could up the mhz on 65nm. The 65nm K8's are a bit enhanced from 90nm according to die shots. It looks like AMD will try to up the mhz instead like IBM is in the POWER6.
K8L comes out still in 2007. Just like ppl didn't think 65nm would come out until the 2nd half of 2007, now its coming out in the 4th Q of 2006. K8L more around the 1st or 2nd Q at the most of 2007. Engineering samples of 65nm K8's have been out since may, the 1st were made in fab 30 in may. K8L Taped out in Nov of 2005 and should be out in the wild by around Dec 06 in the form of (ES) about the same time when 65nm K8's come out to the public."
I put this up before. But I can't find the plans for K8L that show what the parts of the arc do for referince. So the people that don't understand what parts I am talking about on the core will not understand what I mean. So thats understandable. Half of the people here can't help they can't understand some things. But this is as simple as I could have said it. Sorry if it becomes hard for some. But I try to make it sound as understanding as possible.
This is kind of old of a post tho. But the new links prove K8L is everything we say it will be well almost everybody. It will sertently be faster then Conroe. K8L was made to combat DUO3 actouly.
What do all those numbers really mean you ask? Well if you can't understand them and do the math its really hard to explain only that Conroe can't compete with K8L is the most simplest thing I can tell you strate up mate.
Sharikou said...
"FAB36: 25000wspm, 100 % 65nm"
Seems this link does not agree.
You are assuming 100% from the start of the year, and the image on the bottom of the page clearly contradicts this.
"FAB30: 100% dual core AM2 production"
You are also not taking into account that FAB30 will drop production while ramping to 65nm, though it won't fall below 50%, it still hurts your predictions.
Seems this link does not agree.
These crap are 100% crap. We have AMD's slides from its analyst meeting, was he saying AMD committed securities fraud by lying to investors? FAB30 will cut its 90nm production by 50% in 3Q07. So, we can deduct 25 million dies there. But the total will still be 220 million.
4
The release of the X2 5200+ (2.6GHz) has a TDP of 89W, 24W of which is the addition of 1MB of cache.
90nm...89W - 48W (2MB cache) = Processor TDP no cache 41W.
[0.72 = 65*100/90]
65nm...(41W*0.72)30W Dual core = 60W Quad core no cache.
65nm Cache (24W*0.72)17.3W per MB * 4 = 69W for cache.
Quad core at 2.6GHz 60W + 69W = 129W
[0.46 = 1.2*100/2.6]
Quad core at 1.2GHz (60W*0.46) 27W + 69W = 96W
Where do you learn this math?
Cache isn't so power consuming, just look at mobile processors like Turion X2, 31W for 2x256kb@1.6GHz and 35W for 2x512kb@2.0Ghz, let's get the last one to do a simple math:
35W + 4W + 4W (to add 256kb+256kb to each core) = 43W
2x43W (four cores now) = 86W
Now, how much the smaller process can reduce the power?
Sharikou said...
"We have AMD's slides from its analyst meeting, was he saying AMD committed securities fraud by lying to investors?"
No, but sh!t happens, hence the statement on the bottom of this page...
Cautionary Statement
This release contains forward-looking statements concerning AMDs plans for future capital expenditures, Fab 30, and its conversion to Fab 38 and Fab 36, including its output and capacity, and demand for AMD64-bit solutions, which are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that the forward-looking statements in this release involve risks and uncertainties that could cause actual results to differ materially from the company’s current expectations. Risks that the company considers to be the important factors that could cause actual results to differ materially from those set forth in the forward-looking statements include the possibility that global business and economic conditions will worsen resulting in lower than currently expected sales; that Intel Corporation’s pricing, marketing programs, product bundling, new product introductions or other activities targeting the company’s microprocessor business will prevent attainment of the company’s current microprocessor sales plans; that demand for computers, and, in turn, demand for the company’s microprocessors will be lower than currently expected; that adoption of AMD64 products by OEMs will not continue to occur as expected; that the company may not achieve its current product and technology introduction or implementation schedules; that the company will not be able to raise sufficient capital to enable it to establish leading-edge capacity to maintain its market positions and that solutions providers will not timely provide the infrastructure to support the company’s AMD64 technology. We urge investors to review in detail the risks and uncertainties in the company’s Securities and Exchange Commission filings, including but not limited to the Annual Report on Form 10-K for the year ended December 25, 2005 and the Quarterly Report on Form 10-Q for the quarter ended March 26, 2006.
http://tinyurl.com/l3qxl
That is Intel, caring about your blog:)
Anonymous said...
"Where do you learn this math?"
This is not my field, and is exactly why I asked others to look at the numbers. I am using numbers from an article I linked to.
What is the main difference between Desktop and Mobile processors?
Isn't it a type of throttle management?
hence the statement on the bottom of this page...
If there is a material adverse effect, AMD is obliged to inform investors. So unless they change their original position, all those crap semi retarded analysis are retarded. For instance, AMD said next gen quad core in mid 2007. A whole bunch of crackpots said it would be 2008. Who is right? Huh? Who knows more?
Charlie@INQ's previous insistence that AMD wouldn't have quadcore until 2008 was quite stupid. AMD put the writing on the wall, next gen quad mid 07. He insisted it would be 2008. He heard sth, but he didn't use his brain.
Same apply here on this half witted FABtech dude.
hence the statement on the bottom of this page...
If there is a material adverse effect, AMD is obliged to inform investors. So unless they change their original position, all those crap semi retarded analysis are retarded. For instance, AMD said next gen quad core in mid 2007. A whole bunch of crackpots said it would be 2008. Who is right? Huh? Who knows more?
Charlie@INQ's previous insistence that AMD wouldn't have quadcore until 2008 was quite stupid. AMD put the writing on the wall, next gen quad mid 07. He insisted it would be 2008. He heard sth, but he didn't use his brain.
Same apply here on this half witted FABtech dude.
Does anyone actually knows if this 60/100 percent increase is per core or just the K8L quad versus modern day X2?
"How do we know 60% integer and 200% floating point? Is that over current AMD or Conroe?"
Those are theoretical best-case improvements over the current K8. You will never see such performance boost in real applications (not even in 'realistic' benchmarks).
200% floating point is simply due to 2x 128-bit SSE ALUs with a better implementation. Also K8L has 4 x86 decoders, up from 3 in K8 (33%), plus a better this and a better that - that is, 10% here, 10% there and 5% elsewhere blah blah blah (you get the idea) - it sums up roughly 60%.
I have to say that, while more than 2x floating performance in K8L compared to K8 is quite possible, the 60% integer performance increase is too optimistic. I believe it would be lucky to see K8L perform 20% - 25% better than K8 on single-threaded integer benchmarks at the same clockrate.
"Zram is in K8L, the L1 L2 and L3 is 4x smaller in the die shots then K8 L2 but the same size in Kb such as 512kb L2. Sram would take up far too much space to add that much L3 L2 and L1 all on the same die when its smaller then K8 dies."
AFAIK, ZRAM in K8L is still purely guesswork from AMD fans. ZRAMs are small, but they are slow. I vaguely remember its access time around 2ns or so, which means it operates at 500Mhz at best.
ZRAM's strength is its small size. A ZRAM cell is about 1/6 the size of an SRAM, thus a 2MB L3 cache of ZRAM would have only 1/3rd the size of four L2 caches in K8L. That doesn't seem logical, and it doesn't seem the case from the layout picture. Had AMD used ZRAM, it would have had put more (say at least 4MB) on the die. 45nm ZRAM seems even more unlikely.
2 enumae:
taking your link into consideration (make my personal viewe more realistic):
at end of 2H 06 ramping is 10 k wspm (lets assume this is the the output for dezember)
lineary increasing to 20 k in end of 07, with additional stock of 5 k from chartered in 07 per month.
Then it will come up for ~ 200K wafers for 2007.
With DualCore-Equivalent of 500 per wafer, we can count for 200k x 500 = 100 000 K -duals-
= 100 M -duals-
= 50 M -quads- "roughly"
At 200$ per Quad -which chould be cheap, at least affordable- it would make up for 10 B $ in sales.
With actual output of ~ 4-6 B $ for Fab30 i can count for 15 B $ sales in 2007.
Ati may make up for some ~ 2 B$ too.
In Sum ~ 17 B $, for sureness (or - ATI) lets say :
15 B $.
Compared to NOW (~6 B sales in 2006 ) that would take a bunch of 10 B$ from intel (sales in 2006 ~ 40 B$) or 25 %.
There is to put in the "intel-factor", that intel in its sales has moboes and chipsets too.
That way, the the "amd-take-off" works on processors. We then may see, that the sales-take-off of 10 B $ may take off 1.5 times 25 % (or even a bit more) off of the processor sales at intel.
For simplicity say : There is a amd-take-off of 35 %.
ON THE FINANCIAL SIDE:
Then think over :
Every unsold intel-cpu is
-
potentially an unsold intel-chipset !!
potentially an unsold intel-mobo too !!
That means , 10 B $ sales more at amd in 2007 is NOT VERY unlikely to have ONLY an impact of only 10 B at intel !!
10 B $ at amd may come up to -10, -15 or -20 B -effect at intel.
Further may add some income at non-intel-cpu chipmakers, therefor i see some support here.
NOT ONLY SUPPORT, for them a chance to grab marketshare too.
A sales decrease at intel of ~ 25 - 35 % may lead intel into greater restructuring in 2007 and on. that then will be their main job.
ON THE CPU SIDE:
If 75% of sales (40B) at intel is cpu business (=30 B)a take off of 10 B $ would mean a loss of a FURTHER 35% in marketshare.
If in worst case amd has NOW ONLY 20 % in 2007
AMD CAN REACH 55 % of marketshare.
-just if the fu+++n quad is a micron better than conroe-
OK ! lets go down to 50% !!
why not -10% for surness ?? :-)
INTEL / AMD then pari,
Now with intel MCAP = 110 B
AMD with 12 B
The dell-deal might be about " if u are not in now, then u will be out then "
which would cause a marketshare loss of 10 % worldwide for dell in 07 / 08 and forever.
EARNINGS for AMD 07
People increase is poised at 1 k at fab36
-
Not that much overall, may cost 1 B$
-
Ati may feed itself (weather a share loss of 20 cent or not)
-Fab30 may pay material costs
-Fab 36 is pure earnings
-10 B$ earnings
;-) ;-) ;-)
lets subtract a massive 50 %
just for sureness, to please ( NO : AMUSE )everybody
-> 5 B $ eanings
->500 M shares
->10 $ per share
PE = 10 - 20
shareprice 100 $ - 200 $
We have a wonderfull sunny summer sunday this morning in germany.
I like it, looks like a killer chip, Hey are AMD gonna demo it before end of 06 as they promised??
You enjoy pointing out that Core 2 production is still ramping up, and that Intel is still producing a lot of Celeron Ds/P4s/Pentium Ds.
When K8L comes out, will that instantly make up 100% of AMD's processor production?
Nah, I didn't think so.
http://tinyurl.com/l3qxl
^^
I thought this was a family blog:)
When K8L comes out, will that instantly make up 100% of AMD's processor production?
It's called APM3.0. AMD can push a switch, and everthing becomes K8L. FAB30 will be dedicated to K8(AM2 and 939) production.
Are you ready Sharikou?
Sharikou said...
"Same apply here on this half witted FABtech dude."
You just do not like the fact that if it doesn't show pro-AMD, it is not a valid source... lol
I am going to look at the June 1, 2006 Technology Analyst Day PDF.
"Fab 36 expanded to 25K wafers/month by Q4 2007." page 4 of 28
"Fab 36 65nm crossover expected in 1Q 2007, full conversion to be achieved by July 2007." page 6 of 28 (I am interpruting this as greater than 50% 65nm)
So lets re-evaluate your statements, using AMD only...
"FAB36: 25000wspm, 100 % 65nm"
Fab 36 at about 15000 +/- wspm (December assumption) expected to be 25,000 wspm.
Lets just assum they are already 100% 65nm.
25,000 - 15,000 = 10,000wspm divided by the 12 month transition, an increase of 833wspm.
Example...
(15,000+(833*1))*540=8,549,820 (January)
(15,000+(833*2))*540=8,999,640 (February) etc...
8,549,820(January)
8,999,640(February)
9,449,460(March)
9,899,280(April)
10,349,100(May)
10,798,920(June)
11,248,740(July)
11,248,740(August)
12,148,380(September)
12,598,200(October)
13,048,020(November)
13,500,000(December)
Annual 65nm parts 2007 at 100% 65nm = 131,838,300 dual core candidates vs your 160,000,000.
January thru June (at 100% 65nm production) = 57,596,400 dual core candidates.
July thru December (when 65nm conversion is achieved) = 74,241,900 dual core candidates.
Lets just assume they will be at 60% 65nm in January then ramp to 100% 65nm July while taking into account ramping to 25,000wspm.
5,129,892 (January) 60%
6,029,758 (February) 67%
6,992,600 (March) 74%
8,018,416(April) 81%
9,107,208(May) 88%
10,258,974(June) 95%
January thru June ramping to 100% 65nm = 45,536,848 dual core candidates.
Taking into account ramping up to 100% by July = 119,778,748 dual core candidates vs your 160,000,000.
Granted I am assuming the 60%, but your numbers are just wrong.
Fab 30... To be continued.
"It's called APM3.0. AMD can push a switch, and everthing becomes K8L. FAB30 will be dedicated to K8(AM2 and 939) production."
He didn't ask if AMD can do it, he asked if it will do it.
" Anonymous said...
http://tinyurl.com/l3qxl
That is Intel, caring about your blog:)
8:55 PM, September 16, 2006 "
this spam hurts..
seems intelfanboys can come with some real facts lately .. o_O
http://tinyurl.com/l3qxl
See, he's not even excited:) And what facts do you/Sharikou have? 60% in 'integer speed', 200% floating point? How about some real numbers?
Something tells me AMD is feeding Charlie some serious Charlie-bait.
Nothing in Charlie's article makes sense. Not the features, not the timetables, not the confusion that will be generated from AMD's approach.
AMD has not fielded ONE innovation since the original Opteron. While it is nice to talk about K8L (and Rev G, H, etc.), it is ridiculous to jump to the conclusion that AMD is an innovative company based on one chip design.
When AMD actuallys ships something new (vs. cutting prices and talking about vapor products), this blog may get interesting.
The fact that the Dell of microprocessors finally teamed up with Dell... well, it was way too late to be that interesting.
Dell's machines with AMD are non-innovative. Just more cheap machines from Dell.
I am sure the Wall Street analysts are waiting to see something of substance from AMD. Maybe the whole world is waiting.
Didn't AMD said something about ~300m transistors in K8L quad core?
If they did then L2 and L3 simply has to be made of ZRAM, just count it for yourself: 6x1024x1024x4 (in reality theres more transistors than that in 4 MB of SRAM, cause those are just the holders we counted)
Isn't 6 transistors per bit?
I mean, the 6x1024x1024x4 give the number of transistors for 4Mbits, for 4MBytes we should multply it by 8 (9 with parity):
6x1024x1024x4x9 = 226 million
"Didn't AMD said something about ~300m transistors in K8L quad core?
If they did then L2 and L3 simply has to be made of ZRAM, just count it for yourself:"
I don't know how many transistors there are going to be in K8L. If the number is indeed around 300M, then the shared L3 cache is likely made of ZRAM. But 300M for quad cores is too small a number, IMO. The X2 with 1MB L2 cache already has 233M transistors; for the same die size, going to 65nm would give K8L at least 400M transistor budget.
Even if AMD has ZRAM ready for the shared L3 cache, IMO the L2 cache will not be ZRAM, simply because ZRAM is too slow.
"AMD has not fielded ONE innovation since the original Opteron. While it is nice to talk about K8L (and Rev G, H, etc.), it is ridiculous to jump to the conclusion that AMD is an innovative company based on one chip design."
Well, if we follow your logic, then we shouldn't call Microsoft an innovative company since Windows XP 3 years ago, nor Apple an innovative company since iPod since 2001, nor Qualcomm an innovative company since its first CDMA cellphone.
If you don't agree with what I said above, then you probably know that there ARE revisions and innovations over the lifetime of a product line (even in the case of Microsoft). Also, a company can well be called innovative because it had been innovative (e.g., true x86 superscalar in K5, CISC-to-RISC in K6, 3DNow, and Athlon), and will come out with more innovations (native quad-core, K8L) again.
Unless of course your idea of "innovation" was only fed from some big money's advertisement campaign.
(native quad-core, K8L)
If K8L is 'innovative', then so would Core 2:)
And I'm sure it took a rocket scientist to think of native quad core. Speaking of which, Intel has been 1-2 quarters early recently with products recently. If AMD does not get 65nm worked out, then there is a very big chance that Intel will deliver to the market native quad core.
Hey Sharikou...
Just wondering what your response was to the number of dual core candidates?
Just wondering what your response was to the number of dual core candidates?
I wasn't computing the totals for 2007. I was computing the quarterly dies in 3Q07 and extrapoltae for a year. We know AMD capacity will keep rising until 2009 and beyond, reaching 95% of the market at some point. VIA will take the remaining 5%.
"...you pure victim of intel advertisement. The only reason you think AMD didn't came up with something new is because AMD doesn't flash their new toys the same way intel does."
No, dude.
I own several Opteron systems, including a new 4 core 2P system.
And since I bought my very first Opteron -- an Opteron 240 BTW -- there has been nothing innovative from AMD.
Using your brain dead logic, I should count the 8132 as innovative as it fixed a lot of the bugs in the 8131?
Of course, Nvidia is still making semi-buggy chipsets (and shitty drivers) for Opteron. Should I count every new pseudo-stable release from Nvidia as innovation, too?
One can only hope that after buying AMD, that the new company can make higher quality drivers. Of course, compared to ATI, Nvidia drivers look like famous Italian sculpture.
So when AMD hypes up some new chip that will not ship for a year, it does nothing for me. AMD has been hyping K8L for a long time and so far what have they shipped?
There is no Torrenza on the market.
There is no 4x4 on the market.
Opteron DDR2 is slow compared to Opteron DDR
Opteron DDR2 needs more expensive memory (which has gone up roughly 20-25% since Opteron DDR2 shipped).
Overall, AMD is very much like Intel. All marketing. Intel had a good design -- Pentium Pro. So it rewarmed this designed as Core Duo. I am not under any illusions about Intel.
But as an AMD owner, all I can say is for the past 5 years I have seen a lot of hype and not a lot of innovation.
"Good point. So maybe ZRAM for L3 and SRAM for L2 is how they going to do it?"
Take a look at the die shots. The caches take up roughly half of the die space. I'd say its safe to say they are not using zram with first generation K8L's.
Also K8L has 4 x86 decoders, up from 3 in K8 (33%)
If I am not mistaken, K8L also has only 3 decoders, not 4. I distinctly remember reading that in multiple articles.
"There is no Torrenza on the market."
You are just ignorant. Torrenza is for the next generation of Opteron; of course as it is supposed to be, it is not on the market right now.
However, there are already FPGA coprocessors that could drop in socket 940.
"There is no 4x4 on the market."
You can't wait for it uh? Don't worry, it WILL be here by the end of this year. But I'm sure even then you won't call that an innovation.
"Opteron DDR2 is slow compared to Opteron DDR"
Where did you get this silly idea? Current AM2 isn't as fast as expected, but it is not slower than S939.
"Opteron DDR2 needs more expensive memory (which has gone up roughly 20-25% since Opteron DDR2 shipped)."
Opteron DDR with slow memory would only run slower.
"Overall, AMD is very much like Intel. All marketing. Intel had a good design -- Pentium Pro."
Again you've only shown your ignorance. It seems owning Opteron boxes didn't help you understand computer in general or K8 in particular any better.
If you really think the later Opteron boxes have no innovation what so ever, why don't you exchange them for some older Opteron boxes from somebody's aging stock? They will certainly thank you.
"And I'm sure it took a rocket scientist to think of native quad core."
As matter of fact, it does.
People feeding on amateur websites will never grasp the complexity involved in a native design. AMD touted it for a good reason.
At least we know that Intel is also trying to do it, but won't get it done until late 2007 or early 2008. ;-)
Edward Greenlover said: "You can't wait for it uh? Don't worry, it WILL be here by the end of this year. But I'm sure even then you won't call that an innovation."
No, dude.
2P on the desktop is not an innovation.
Only a foaming-at-the-mouth AMD cultist thinks taking something well over 10 years old in the enthusiast market and slapping a new coat of paint on it is "innovation".
The only reason AMD's new marketing slime driven "4x4" 2P is not here today is that AMD is very anti-customer and very weak on execution.
AMD's anti-customer attitude is what created all the crippled desktop chips that don't have the HT links to do 2P.
And AMD's poor execution is the cause of what is taking so long to add those HT links back in and make it work.
All in all, "4x4" is just a dumb joke that only AMD mouth foamers laugh at. The rest of us are building and running real 2P systems (and have been doing so for a long time).
core2dude said: "If I am not mistaken, K8L also has only 3 decoders, not 4. I distinctly remember reading that in multiple articles."
Then you are probably mistaken.
The Rev.H ('K8L' core) has 4 complex decoders. See this Geek.com page. Now I know it won't convince you; so follow this link, too, and look at the four vertical yellow box at the middle toward a quarter right place.
If that still doesn't convince you, that your distinct memory still serves you better than anyone's analysis, I have nothing further to say.
"The only reason AMD's new marketing slime driven "4x4" 2P is not here today is that AMD is very anti-customer and very weak on execution."
Anti-customer? What are you talking about? Are you color blind that you mix up blue and green? How is AMD anti-customer to announce its roadmap/plan for the enthusiast market by the end of this year?
AMD is not even marketing 4x4 like Intel did to Core2Duo 6 months ago.
"AMD's anti-customer attitude is what created all the crippled desktop chips that don't have the HT links to do 2P."
All Athlon64 processors have 3 HT links. Want proof? Follow these steps:
1) Go buy an Athlon64(X2) box
2) Install Windows and AMD's CPUInfo utility
3) Run the utility and count - HT0, HT1, and HT2.
What will you say now? That AMD's CPUInfo utility is lying about the processor capability?
"Only a foaming-at-the-mouth AMD cultist thinks taking something well over 10 years old in the enthusiast market and slapping a new coat of paint on it is "innovation"."
And only an ignorant retard would think NUMA being the same as UMA SMP. Hey, you don't need to love NUMA, but it is still an innovation, on die, integrated, for x86-64 processors.
Edward said...
"AMD is not even marketing 4x4 like Intel did to Core2Duo 6 months ago."
They don't have or would spend the money to market it, plain and simple.
""AMD is not even marketing 4x4 like Intel did to Core2Duo 6 months ago."
They don't have or would spend the money to market it, plain and simple."
enumae, please don't take my words out of context. Whether AMD have marketing $$$ or not, AMD doesn't market 4x4 like Intel did with its pre-releases; AMD doesn't hype a product only to make 25% of those after 6 months after release and 10 months after marketing. Thus AMD was not nearly as anti-customer as Intel.
Some moron said otherwise, and I was refuting his silly comments. How can a company be anti-customer when its customers can perform drop-in upgrades 3 years after the previous generation? I did that, my friends did that, hell, even DOE did that. Expect to do so with K8L on 4x4, too.
Edward said...
"enumae, please don't take my words out of context."
Actually I didn't.
I was simply stating that AMD does not have or is willing to spend the money on marketing 4x4.
It is a niche market, enthusiast will be there marketing as will review sites.
As for your comments about...
"How can a company be anti-customer when its customers can perform drop-in upgrades 3 years after the previous generation?"
I never said it wasn't.
"It's called APM3.0. AMD can push a switch, and everthing becomes K8L. FAB30 will be dedicated to K8(AM2 and 939) production."
Let's put some perspective on your quotes as you appear to have the Si manufacturing experience of a third grader:
Typical cycle time for a lot is ~12-13 weeks; so if they flip the switch things come out ~1 quarter later; you can;t convert a K8 lot ionto a K8L lot!
It would be insanely stupid to swicth over 100% "instantaneously" as there will likely be additional steppings after the initial K8L chips ship - you will therefore see a graded transition to K8L, not a delta function.
It is unlikely that K8L will be running on 90nm process therefore until F36 undergoes full conversion to 65nm (which I believe is somewhere mid-end '07); you will either have a bunch of 90nm tools sitting idle or AMD will still be producing K8 out of F36 toward the end of 2007.
Oh and it's not APM3.0 that enables the conversion between product...but that's a story for another day.
"Oh and it's not APM3.0 that enables the conversion between product...but that's a story for another day."
Is it a story for another day, or a story that you don't know?
According to AMD, one of APM's benefits is this:
"Because we can make rapid in-fab adjustments to what products we're producing and how those products operate, AMD can closely align our production with your supply chain requirements."
If that doesn't sound like more efficient product mix, I don't know what else it could mean.
Of course, no production switch can be instantaneous, but in terms of APM 3.0, the production can be controlled at the wafer level (AMD's official claim).
I expect Fab36 finish the first batch of K8L by the end of 2Q 2007, and fully converted to 65nm cores by the end of 3Q 2007. In the mean time, Fab30 will produce 90nm chips, and undergoes 65nm/45nm upgrade in 2008 and later.
Some monkey said
"It's called APM3.0. AMD can push a switch, and everthing becomes K8L. FAB30 will be dedicated to K8(AM2 and 939) production."
Do you have any experience in the fab, manufacturing high performance products? If you don't shut the F up.
You are like the PhD pretender who take others pumping as truth because you like the answer..
Tell me in simple terms what APM is and why it lets you switch back and forth or quickly with no need for downstream or end of line validation... I await..
Opps that wasn't in the press release.. nuf said you idiot
"Is it a story for another day, or a story that you don't know?"
Edward - at what point in the Si process flow do products start diverging? This would be near STI patterning - which defines active Si regions/transistor layout which will differ from product to product. Off the top of my head this is ~ step 3 or 4 out of many hundred steps in the process flow (starting Si, pad oxidation, nitride deposition, STI patterning). After this the prodcut is what it's going to be - APM or any other technology in the world cannot convert this into another product - it's like staring to build an SUV frame and saying with APM I will now make this into a sports car.
APM does not determine product mix in the fab (and cannot magically convert one product into another). For the folks who have fab background experience, you'll understand this, for the folks who don't...keep drinking the coolaid!
What APM does (as do most other fab process control systems without the cool names) is control processing for a given tool and provide feed forward / feedback to tune process recipes and get better control over process conditions (whether it be defects, uniformity, specific parameters like Vt, Rext, Idsat, Rs, FCCD, DCCD, etc..) to get better overall performance on a wafer and/or yield.
...or it coud be a story I just don't know as you suggest.
Re-read the quote you provided...it said APM can make adjustments to products not the ability to SWITCH between products (i.e affect product mix)
"This would be near STI patterning - which defines active Si regions/transistor layout which will differ from product to product. Off the top of my head this is ~ step 3 or 4 out of many hundred steps in the process flow"
True. Just like your car-making analogy, basically this is a pipeline. Once something starts being made from the first stage, it keeps being there until it goes out of the pipe.
Lets assume that, among many other things, APM has the ability to dynamically control the number of masks used, or layers made in the lithography. So to switch production, the pipeline does not need to wait for its current contents to flush; it can start a different product after only a small number of bubbles in the pipe.
Without APM, the pipeline may need to be flushed, reconfigured, and restarted. Yes, in this case there will be 10-12 weeks delay during product switch. With APM, it's conceivable for the pipeline to come out 65nm Rev.G today, and 65nm Rev.H only a few days later (i.e., both products are in the pipe at the same time for the past 10 weeks or so).
Anti-customer? What are you talking about? Are you color blind that you mix up blue and green? How is AMD anti-customer to announce its roadmap/plan for the enthusiast market by the end of this year?
Yeah right, read this for yourself.
http://www.ngohq.com/home.php?page=articles&go=read&arc_id=112
may this site is one of it :)
"Yeah right, read this for yourself.
http://www.ngohq.com/home.php?page=articles&go=read&arc_id=112
may this site is one of it :)"
Sorry, I have to call that webpage FUD and you retard.
As a matter of fact, the "viral marketing" has nothing to do with AMD's virtual tradeshow. It has nothing to do with people visiting a particular website. It is just the marketing company spreading similar articles on different forums.
Call it spamming or call it flooding. At the end of the day, anyone can do that. Just register multiple accounts on the forums and copy & paste (with minor edit if you like).
Again, it is nothing viral as we knew in our common sense, and it has nothing to do with AMD's virtual tradeshow. Now I understand some people don't have the intelligence to know a FUD when they see one - they are called retard for good reasons.
"With APM, it's conceivable for the pipeline to come out 65nm Rev.G today, and 65nm Rev.H only a few days later (i.e., both products are in the pipe at the same time for the past 10 weeks or so)."
I'm not sure I fullly understand this comment (so my answer may not make sense)
Multiple product types are in the "pipeline" in the fab in EVERY factory in the world (with or without APM). Once the prdocut is started however you cannot convert it from product A to product B. People keep saying APM allows more product mix flexibility, but that is not what APM is utilized for - it is utilized for process/performance control.
Furthermore as it takes ~12-15 weeks for a lot to process completely through the fab, multiple products are run in parallel (i.e you don't wait for "rev G" material to get completely out of the fab before starting "rev H" material). This is done by running a different recipe on generally speaking the same set of tooling and this is controlled by factory automation (which tells each fab tool what recipe to run when the lot arrives via OHV at the tool). This is something every 300mm fab in the world does and is not an APM thing.
As an example IBM has >15000 masks/reticles in their fab; TSMC >15000 - do you think they have that many litho tools? Or perhaps litho tools are capable of switching between mask types and product types on the fly. The same can be done with CMP, ILD, Implant, etc... This is not a unique capabilty that APM enables!
"Lets assume that, among many other things, APM has the ability to dynamically control the number of masks used, or layers made in the lithography."
The number of layers made in lithography is governed by the product design and technology node (APM cannot change the number of masks used for a specific product). This is defined by the number of metal layers, the number of Vt splits, implants, gate, etc... The process flow is the process flow - APM can't just eliminate processing steps as you suggest. What it can do is affect wafer/lot velocity through the fab by intelligent feed forward/backward meaning less metrology or less impactful metrology which could improve overall cycle time - this was evidenced by AMD's technology day presentation on days per mask layer. But to state APM can control product mix or adjust things like the number of litho steps is just ignorant of how a fab operates.
"Without APM, the pipeline may need to be flushed, reconfigured, and restarted. Yes, in this case there will be 10-12 weeks delay during product switch. With APM, it's conceivable for the pipeline to come out 65nm Rev.G today, and 65nm Rev.H only a few days later (i.e., both products are in the pipe at the same time for the past 10 weeks or so)."
Uh...no...this would mean every IC manufacturer without APM would have all this idle time when swtiching between products? What about a company like Renasses ot a foundry like TSMC which does THOUSANDS of products? The flushing/reconfiguring you describe is exactly what happens when switching between TECHNOLGY NODES (and this is only on a certain percentage of the tooling, not all of the fab tooling) not between product types on a given technology node.
"What about a company like Renasses ot a foundry like TSMC which does THOUSANDS of products?"
Foundries like TSMC put multiple chips on a single wafer. To do that, they dictate the technology, the parameters, and number of metal layers your chip is going to be. They offer customized libraries for their processing on a particular pipeline (they have multiple pipelines per fab).
This is entirely different from Intel making Netburst/Conroe or AMD making K8/K8L on the same pipeline. Even if they all use 65nm processing, for various reasons they most likely don't have the same number of layers or even physical libraries.
In other words, TSMC tells you what you can have when you send your design to them; you rarely if ever have the ability to ask them change a parameter for you. OTOH, CPU manufacturers change their fabs for a new processor design in order to meet the performance requirement of that processor.
AMD without APM and a single 65nm production fab WILL suffer 10-12 weeks delay when switching from K8 to K8L. AMD with APM 3.0 won't.
"The number of layers made in lithography is governed by the product design and technology node (APM cannot change the number of masks used for a specific product). "
You don't understand what I said.
Between K8 and K8L, or between Netburst and Conroe, there could be enough chip design differences that require different parameters on lithography.
APM is good at dynamically changing and monitoring those parameters, as required by each wafer, by increasing the yield during switches. So yes, you can have one wafer making Conroe and the next making Netburst, but you really want to group all Conroe wafers together or you won't get good yield. APM helps lessen the number of consecutive wafer of the same design you have to run to reach a good yield. So you can get better product mix.
As for what you said, it's just a pipeline. Tell me how TSMC would make chips of one parameter set on a wafer and make chips of another parameter set on the next? Many of those parameters even requires manual adjustment - which is one of many things that APM does better.
Sorry, I have to call that webpage FUD and you retard.
As a matter of fact, the "viral marketing" has nothing to do with AMD's virtual tradeshow. It has nothing to do with people visiting a particular website. It is just the marketing company spreading similar articles on different forums.
Call it spamming or call it flooding. At the end of the day, anyone can do that. Just register multiple accounts on the forums and copy & paste (with minor edit if you like).
Again, it is nothing viral as we knew in our common sense, and it has nothing to do with AMD's virtual tradeshow. Now I understand some people don't have the intelligence to know a FUD when they see one - they are called retard for good reasons.
I'm not sorry to call you moron.
My point is, AMD hiring some company to spam the forum which is not ethical, cheating and disturbing the forum visitor with information that they do not need. if you were to say AMD did not know about when they hire the company, then I call AMD ignorant and stupid. Either way, it is a marketing, and it is a BAD one.
"My point is, AMD hiring some company to spam the forum which is not ethical, cheating and disturbing the forum visitor with information that they do not need."
It is unethical and cheating only if the articles post to those forums are unethical and cheating.
You never go to a forum and expect to find exactly what you need. There is no such contract that you have to post what others need to a forum. And why won't people want to take a look at AMD's virtual tradeshow, unless they were die-hard Intel fans?
When we turn on TVs, read magazines, or even walk on the streets, we see numerous silly Intel ads such as "xxx makes your Internet faster," "yyy brings the virtual experience to your lap." Do you think we need those? Do you think they are true? Have I called Intel unethical for that?
Intel is unethical for its monopolistic marketing strategies, for the way it prevented open competition. Had not been AMD, Intel would sell you $1k Itanium processors or $500 Pentium-4 craps to this date. THAT's unethical.
Again, the forum spaming is nothing viral. It's probably not even bots posting, but real human doing that.
"Tell me how TSMC would make chips of one parameter set on a wafer and make chips of another parameter set on the next?"
Well, let's see how many examples would you like?
Cu CMP: Endpoint on the system will automatically stop the process when the Cu is cleared and Ta/TaN barrier is reached; thus you can polish a metal 1 layer on a K8L lot followed by metal6 layer on a Kkk8 lot followed by a metal 3 layer on some GPU chipset all without the magic of APM? The amount of overpolish will then in turn control via and line resistance - all done on the tool level.
How about implant - I can change the does energy (in the tool recipe) to change the junction depth profile of a dopant species for one product vs another (on lots that are cascaded consecutively). This could be used to change Vt or fmax (depending on dopant species and process flow step as there are over 15 implant steps in a modern process flow)
I can load in a batch of wafers in to a VDF and grow a 12A gate oxide for a high performance part and then unload those wafers,load in a new batch and run a 20A gate oxide for lower power devices. This which would impact jox, tox (leakage and elecrical thickness)
I can take a 193nm stepper and run a Conroe lot, change the reticle (<20min) and then run a Merom lot, change the reticle again and run a Woodcrest lot. Of course there is a small downtime hit to change reticles so you generally have cascade requirments of a certain # of lots but again this is a fab operational design rule and has nothing to do with APM.
It is clear from you comments you never have set foot in a fab and don't know how one operates. The ability to cascade lots and manage product mix has very little to do with APM.
As I have given you a few examples, perhaps you can give me just one specific example of how APM improves product mix efficieny? (please provide some specific detail)
"As I have given you a few examples, perhaps you can give me just one specific example of how APM improves product mix efficieny? (please provide some specific detail)"
Which would be maintaining good yield in all your examples above.
Your "examples" only showed one thing: it is possible for a fab to make different chips. As a matter of fact, I didn't say otherwise.
The only "difference" is that, from the tone of your speaking, I assume in your fab changing doping level or reticle doesn't affect yield a bit? -- you must be joking...
Well but if that was true, then apparently you don't need APM.
"It is clear from you comments you never have set foot in a fab and don't know how one operates. The ability to cascade lots and manage product mix has very little to do with APM."
Ah I missed this part the first time I read your comments.
What's really pity is, for all those technical terms that you shoot out, you was not capable of -
1) understanding what I was saying
2) understanding what's most important to a fab
The most important thing to a fab, given a specific node, is yield. You can change gate thickness from wafer to wafer; you can polish metal1 and metal6 at the same step; and you can load different masks whenever you want. But by doing so, you will disrupt the optimal flow of the wafer processing, and you will suffer worse yields. Even worse, you won't be able to know exactly where went wrong when 2 weeks later a big number of your dies do not test okay.
Sure you might be able to work as a fab technician, but if you run a fab like what you said to increase product mix, you'll only run out of business faster.
And if you thought APM could not help optimizing the wafer flow, thus increase/maintain yield during parameter changes, then you are either stubborn or ignorant.
it is unethical and cheating only if the articles post to those forums are unethical and cheating.
wow, anything with AMD is not wrong ...
spam is a wrong thing to do. Just because i know you are more than 30's , does that give me the right to spam your mail box with viagra ads? i'd think it might (with quite some high chance) that it is good for you.
if you have hard time to understand the word 'viral marketing', here is the link for you. read it and stop whining. Stop calling people retard when you are a moron of not bale to understand or even search for the meaning.
http://en.wikipedia.org/wiki/Viral_marketing
"Just because i know you are more than 30's , does that give me the right to spam your mail box with viagra ads?"
So what does AMD spam? Viagra ads? False information? How many is the spam? 10k? 5k? The 'spam' forced any forum viewer to read the article?
So some marketing employee writing about a website they're marketing, on a dozen forums, is spam and viral marketing?
Think straight, if you can, please.
"The 'spam' forced any forum viewer to read the article?"
And why would a company that offers viral marketing/spam do this for free when they could charge AMD? AMD has no reason to tell the truth, not like they're breaking any laws.
Spam email doesn't force you to read it, it's still spam
"Sure you might be able to work as a fab technician, but if you run a fab like what you said to increase product mix, you'll only run out of business faster."
Yet somehow TSMC manages to stay in business and they somehow manage to do this without APM 3.0 magic beans. You asked for examples - if you actually READ my response you'll see I was juts giving examples of how you DON'T NEED 10-12 weeks (without APM) to crossover between products (it can be done in minutes). Of course there are efficiencies in batch size cascading (in certain areas of of the process flow; in others contrary to what you may believe it really doesn't matter - CMP, EP, ILD dep, barrier seed to name a few that are fairly proudct insensitive). There's also a process known as dummification which attempts to take out pattern (and product) sensitivies to various different products, but then again, what do I know.
Again can you provide one SPECIFIC example of how APM3.0 works to improve MIX EFFICINECY (as you have stated) not yield (as I have stated).
As "I'm only a technicican" could you also explain "in this case there will be 10-12 weeks delay during product switch"?
And finally please explain "APM has the ability to dynamically control the number of masks used"... I find this a truly unique breakthrough.
"Yet somehow TSMC manages to stay in business and they somehow manage to do this without APM 3.0 magic beans."
TSMC manages to stay well in business because fortunately they don't do what you described, which WILL bring them out of business soon. Changing gate thickness whenever you want? Changing doping energy as you wish? Are you sure you won't be fired by your manager when the yield comes low?
As I said, it is a common practice for fountries to put different designs on the same wafer. There is really no "switch" as long as all the designs use the same parameters.
And since you didn't know, there are patents on automatic reticle loading/unloading from reticle libraries, for precisely the purpose of dynamic & automatic control of the reticle(s) applied to the different wafers.
I recognize, though, that there are technicians laid off from one of those old, manual, low-yield fabs, and they really don't think APM would make a difference.
BTW, APM is not magic bean, but a name by which AMD calls its fab management technics.
"And since you didn't know, there are patents on automatic reticle loading/unloading from reticle libraries, for precisely the purpose of dynamic & automatic control of the reticle(s) applied to the different wafers."
Actually this s my point - the stuff you describe above has NOTHING to do with APM.
Please give me ONE specific example of how APM3.0 works to improve fab product mix - just one!
"Changing doping energy as you wish?"
Just so I understand you, a typical 65nm process which has 19-25 implant steps (with different implant species and dose energies); - how many implanters do you think there are in a typical fab capable of 20K WSPM?
I guess in your little dream world there is one implanter per implant step (actualluy a min of 2 due to redundancy). Oh, wait there might be fewer and fabs without APM3.0 just decide to have a 10-12 week downtime to re-set up the new implant conditions!
And yes the VDF gate oxide tools only run one recipe!
My point is APM3.0 is not what enables tools to run different products in simple cascading mode - sure you will batch specific product types in certain areas of the fab (ex: a VDF which can run 100-125 generally has farily complex rules as to how many lots are needed before committing it to process; based on lots coming down the pipe and existing WIP.unventory at that specific process step).
But for you to think only APM3.0 does this is just fairly ignorant of how a fab works - once again APM 3.0 is designed to improve performance and yield (not product mix efficiency). Other fabs have other versions of fab automation they just don;t feel the need to toot their own horn like AMD does.
Do you know how product mix in the fab is determined? (When the lot is started! As I have mentioned and you have acknowledged the products start diverging extremely early in the process flow and short of scrapping the lot there is nothing you can do!)
So once again - please provide one specific example of how APM3.0 improves fab product mix efficiency.
"My point is APM3.0 is not what enables tools to run different products in simple cascading mode - sure you will batch specific product types in certain areas of the fab"
You just said what I've been saying from the beginning, didn't you (I actually said "group" rather than "batch")? And why do you want to batch, if "simple cascading mode" is all you wanted/needed?
"I guess in your little dream world there is one implanter per implant step (actualluy a min of 2 due to redundancy)"
Then you guessed wrong. But that doesn't mean wafers of the same technology do not need to be batched for better efficiency or quality control. As you said yourself, there are rules to guard against that.
It seems to me that you're just disagree for the purpose of disagreeing. If however you were really trying to learn more about APM, some AMD technician would be more suitable than me, assuming they are free to disclose the detail.
"If however you were really trying to learn more about APM, some AMD technician would be more suitable than me, assuming they are free to disclose the detail."
I'm not disgreeing just for the sake of disagreeing - YOU have stated APM helps product mix efficiency. I'm asking you to back this up with some actual fact or acknowledge that you are just speculating! As I have seen nothing to back your statement up - I'll just assume you are drinking the APM3.0 coolaid and don't really know how it works.
If this is not the case, step up and describe how it improves product mix efficiency.
"I'll just assume you are drinking the APM3.0 coolaid and don't really know how it works.
If this is not the case, step up and describe how it improves product mix efficiency."
So in your mind maintaining good yield while switching products/technologies does not improve product mix efficiency? Then what is efficiency that you spoke of? Just to remind you (somthing you keep overlood), I was from the beginning not talking about the 'ability' to switch production, but 'efficiency' in doing so.
I would not speak of any detail about APM for AMD. As I said, you should ask them for that, and if you wish, charge them with all the facts and proofs you have, that
1. APM3.0 do not allow "make rapid in-fab adjustments to what products we're producing and how those products operate"
2. APM is nothing but coolaid for drinking.
I only tell you what is publicly available, whether coolaid or not in your opinion, and what is derivable from common knowledge and my personal experience.
"So in your mind maintaining good yield while switching products/technologies does not improve product mix efficiency? "
No - it means you get better yield or better cycle time through the fab - it doesn't change the actual mix of products.
The other flaw in your logic from the beginning, is it is only APM3.0 that has the capbility of doing this or that it is superior; there are numerous fab automation systems (both off the shelf and internally designed ones which do the same thing).
It is impossible to say which system is best because there is no benchmarking - yield is such a function of product design, process window, dies size it is impossible to claim APM3.0 is superior (or for that matter inferior) to any other automation system. Similarly how you cascade different products is also based on your process control and design rules (SPC limits, recipe design, equipment design, tool redundancy, tool capability, etc...) As an example many manufacturers employ such complex dummification/slotting rules these days that even products that are designed significantly differently appear from a process and equopment perspective to be similar. (i.e a metal 8 layer with huge bond pads can be made to look very similar to a metal 1 layer from a process/tool perspective). Or the emissivity of a wafer during an RTP step during S/D anneal can look similar between a mobile and server design.
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